I'm trying to compile my FPGA code following the commands which are present on the wiki.
But, when I change the Verilog code (I'm quite a newbie in Verilog, I prefer VHDL ^^), I have some errors.
For example, I can light only one LED. If I want to light two, I have an error.
This is my code, I wanted to acquire a signal on the E1 connector and generate the same just next to it but I have an error ...
Code: Select all
reg [32-1:0] cpt;
reg [8-1 :0] led_reg;
always @(posedge sys_clk_i) begin
if (rstn_i == 1'b0) begin
led_reg <= 8'h0;
exp_p_dir_o[1] <= 0'b1 ;
exp_p_dir_o[2] <= 1'b1 ;
exp_p_dat_o[2] <= 1'b1 ;
cpt <= 32'd0;
end
else if (exp_p_dat_i[1] == 1'b1) begin
cpt <= 32'd0;
led_reg[0] <= 1'b1;
exp_p_dat_o[2] <= 1'b1 ;
// led_reg[1] <= 0'b1;
end
else begin
cpt <= cpt + 32'd1;
exp_p_dat_o[2] <= 1'b0 ;
led_reg[0] <= 1'b0;
// led_reg[1] <= 1'b1;
end
end
Regards.
Kev' Ttn