Error drivers when compiling FPGA code

[Kev' Ttn]

Hi everyone,

I'm trying to compile my FPGA code following the commands which are present on the wiki.

But, when I change the Verilog code (I'm quite a newbie in Verilog, I prefer VHDL ^^), I have some errors.
For example, I can light only one LED. If I want to light two, I have an error.

This is my code, I wanted to acquire a signal on the E1 connector and generate the same just next to it but I have an error ...

Code: Select all

reg [32-1:0] cpt;
reg [8-1 :0] led_reg;

always @(posedge sys_clk_i) begin
    if (rstn_i == 1'b0) begin
        led_reg         <= 8'h0;
        exp_p_dir_o[1]  <= 0'b1 ;
        exp_p_dir_o[2]  <= 1'b1 ;
        exp_p_dat_o[2]  <= 1'b1 ;
        cpt <= 32'd0;
    end
    else if (exp_p_dat_i[1] == 1'b1) begin
        cpt <= 32'd0;
        led_reg[0] <= 1'b1;
        exp_p_dat_o[2] <= 1'b1 ;
       // led_reg[1] <= 0'b1;
    end
    else begin
        cpt <= cpt + 32'd1;
        exp_p_dat_o[2] <= 1'b0 ;
        led_reg[0] <= 1'b0;
       // led_reg[1] <= 1'b1;
    end
end

Please, help me.

Regards.

Kev' Ttn

[Nils Roos]

As the tools say, there is more than one driver on the exp_p_dat_o signal. If you want to attach logic to it, like you did, you need to remove it from other portions of code where it is already set - in this case the system bus connection.

Code: Select all

//---------------------------------------------------------------------------------
//
//  System bus connection


always @(posedge sys_clk_i) begin
   if (sys_rstn_i == 1'b0) begin
      led_reg[7:1] <= 7'h0 ;
      exp_p_dat_o  <= 8'h0 ;              // <- here: exp_p_dat_o[7:3] <= 5'h0; exp_p_dat_o[1:0] <= 2'h0;
      exp_p_dir_o  <= 8'h0 ;
      exp_n_dat_o  <= 8'h0 ;
      exp_n_dir_o  <= 8'h0 ;
   end
   else begin
      if (sys_wen_i) begin
         if (sys_addr_i[19:0]==20'h10)   exp_p_dir_o  <= sys_wdata_i[8-1:0] ;
         if (sys_addr_i[19:0]==20'h14)   exp_n_dir_o  <= sys_wdata_i[8-1:0] ;
         if (sys_addr_i[19:0]==20'h18)   exp_p_dat_o  <= sys_wdata_i[8-1:0] ;                          // <- also here
         if (sys_addr_i[19:0]==20'h1C)   exp_n_dat_o  <= sys_wdata_i[8-1:0] ;

         if (sys_addr_i[19:0]==20'h30)   led_reg[7:0] <= sys_wdata_i[8-1:0] ;
      end
   end
end

You'd need to do the same if you wanted to use additional LEDs.

[Kev' Ttn]

Thanks you very much ! You're fantastic

I'll test it immediately.