Redpitaya Forum

Posted: **Fri Nov 14, 2014 3:22 pm**

Hello, guys!

I am totally fresh with FPGA, and is struggling to learn it. Besides, I'd appreciate if you could give me some advices.

This summer, one of my friends had tried to compile existing verilog code into bitstream by seperated steps -- Synthesis, Implementation and bitstream generation -- using Vivado 2013.3 GUI. However, command 'make sw_package' always showed error messages, which turned him to full build ( viewtopic.php?f=8&t=42 ).

Here are my questions:
1) Is there update version of RedPitaya documents since June, 2014?
2) As I am using the same hardware as well as software with his, should I try Manual compilation again or just skip to full build? Do thoes issues mentioned in the link still exist?

Thank you!
Ruby

Posted: **Sat Nov 15, 2014 3:34 am**

Hi Ruby,

I am maybe a step or two ahead of you and might be able to help.

I'll be adding another post expressing my disappointment of the entire Red Pitaya road map. But I digress.

I have finally been able to get through the entire Vivado/SDK journey and use progmen.exe to convert the bit file to a bin.

My Vivado is running on win7 64b. After you clone the repo. Search for the RedPitaya.xpr project file and click on it(in a Crt sub dir) . Vivado will open. Click to open the block diagram. Then click generate bitstream. After a few minutes it will complete. Hundreds of warnings.

Most tutorials then have you go to 'File' -> 'Export' and launch the SDK the create some 'C' ARM code. In order to use the SDK you need to set it up. Just follow the 'Eclipse' setup procedure. I simply edited a string in RP's 'generate.c' and verified it would build and run on RP.

So far I have finally been able to add text more text to generate.c, build it, run it in run and debug mode from SDK. It goes into the RP /tmp directory.
I then searchedto find the new .bit file in User/crt... and run progmem.exe to make the bin file.

The wiki says you just copy it to the RP mem card. That's easy enough, but I haven't the foggiest idea what that does. I hope it's the entire FPGA PL code, but I'm not sure. I've read about FSBL, FPGA, UBOOT and don't know how this process fits. The developers did some creative stuff. I guess it's up to us to to reverse engineer it.

BTW I'm using the 13.x recommended version of Vivado.

I feel your pain. Hope I helped at least a little bit.

Regards,
John

Posted: **Sat Nov 15, 2014 8:35 pm**

Hi Ruby, hi John,

Regrettably, the getting started guide is still not fully conclusive with respect to the pre-requisites for all the build steps.
But I believe the original owner of the Wylde account was successful in getting it all set up correctly, and could also perform the step-by-step build. So, following his procedure laid out in the linked thread should get you good results (in a linux environment).

John, if you wonder why the project file and generated bitstream were found in User/crt, it's because that is the place where you cloned the github repository to, I would guess - the example from the wiki uses this path.
You only need to concern yourself with FSBL, U-Boot and devicetree if you want to permanently make your new FPGA design the default (ie. the one that is loaded on boot). When you use the xdevcfg device, these components are not required.
(the FSBL / U-Boot combination is neither unusual nor particularly "creative" in an embedded linux system - even the Xilinx ZYNQ technical reference manual covers it)

I hope I could clear things up a bit, but if not, browse the forum or ask away.
Good luck
Nils

Posted: **Tue Nov 18, 2014 1:37 pm**

Hello, John, Hello, Nils,

Thanks for you help!

John, I know your feelings exactly. I could not help imagining what if there were a tutorial step by step for a simple RP program. And your suggest does help me get a better understanding. Thank you!

Hi, Nils, I have tried a piece by piece build with Vivado GUI and got .bit file in the end. However, the command "promgen" encounters an error:

Code: Select all

promgen -w -b -p bin -o red_pitaya_top.bin -u 0 red_pitaya_top.bit -data_width 32
No command 'promgen' found, did you mean:
 Command 'progen' from package 'tmake' (main)
promgen: command not found

Before this command, I had already done the following:
-installed Vivado 2013.3 and SDK 2013.3 (I checked the dir: /opt/Xilinx/, but I don't know how to check whether it is installed completely)
-typed the following commands:

Code: Select all

source /opt/Xilinx/Vivado/2013.3/settings64.sh
source /opt/Xilinx/SDK/2013.3/settings64.sh

-edited the path to the SDK toolchain in RedPitaya/OS/buildroot/config:138

It may sound stupid, but I really don't know how to fix it, as well as I could not find anything help on the wiki page so far. Thanks advance for any help!

Cheers,
Ruby

Posted: **Tue Nov 18, 2014 4:14 pm**

Hi Ruby,
At the bottom of the FPGA development wiki page is a link to an article that tells you how to get the promgen tool.
(Where can I find the promgen tool?)

I am not quite sure if it is really neccessary, but I do a "source .../Xilinx/14.7/LabTools/settings64.sh" before using it.

Posted: **Mon Nov 24, 2014 4:34 pm**

I'll drop this here, someone may be interested.
There's a commit in the linux-xlnx tree that introduces the capability to program the PL using directly the .bit file; it's included in the 14.7 release (while the redpitaya ecosystem uses 14.6), I've tried to build a newer kernel version without success, but backporting just that patch works.

Here's the hash of the git commit and the header of the commit message for reference:

8bb4738ac

Allows writing a raw .bit file directly to /dev/xdevcfg, without having to process it using bootgen -split.

Posted: **Mon Nov 24, 2014 10:08 pm**

Thanks a lot for finding that out, the to and fro with the promgen was getting on my nerves^^

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