I am new to FPGAs and have been working with the documentation to build a .bit file so that I can modify one of the red pitaya modules.
I set up a development environment in linux 64bit RHEL6 with an installation of Vivado 2014.3 (the free one). I can open my XPR file and build an implementation. Unfortunately, the implementation has timing errors - the Timing Summary report flags the "adc_clk" in red with a TNS of -24.603 ns. Since I am new to FPGAs, I don't really understand what this means nor would I expect an error since I am working with a fresh GIT pull and have modified no code.
I can't generate a bitstream because of the timing error.
I have also failed the command line build ("~/git/RedPitaya/FPGA>> make") on a console with the Vivado settings64.sh script sourced. The first error was like this:
[qoute]
ERROR: [Common 17-69] Command failed: Run 'synth_1' needs to be reset before launching. The run can be reset using the Tcl command 'reset_run synth_1'.
[/quote]
After I typed in "reset_run synth_1" much much more output was produced and eventually there was an error writing the bitstream. The output was copious but here is a snippet of what seems relevant to me:
Can anyone help me figure out what I've done wrong?INFO: [Drc 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /users/kmclewin3/git/RedPitaya/FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1/red_pitaya_top_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
<snip>
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 8 threads
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[0] is Single-Ended but has an IOStandard of TMDS_33 which can only support Differential
<many of these errors>
<snip>
WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP i_asg/i_cha/dac_mult_reg/dac_mult_reg input A is not pipelined. Pipelining DSP48 input will improve performance.
<many other warnings>
<snip>
INFO: [Vivado 12-3199] DRC finished with 10 Errors, 47 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
while executing
"write_bitstream -force red_pitaya_top.bit -bin_file"
INFO: [Common 17-206] Exiting Vivado at Thu Nov 20 17:24:09 2014...
[Thu Nov 20 17:24:12 2014] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:27 . Memory (MB): peak = 1034.625 ; gain = 0.000 ; free physical = 1126 ; free virtual = 5731
# close_project
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Nov 20 17:24:12 2014...
<snipping out the makefile's failure to recover>