Programming FPGA issue

[amvasil]

Hello!

I'm trying to add a digital generator to E1 connector. Digital pins seem to be driven inside red_pitaya_hk.v file. So, I added this code:

Code: Select all

reg [10-1:0] pg_counter;
initial begin
    exp_n_dir_o[7:6] <= 2'b11;
    pg_counter = 0;
end
always @(posedge sys_clk_i) begin
    pg_counter <= pg_counter+1;
    exp_n_dat_o[7] <= pg_counter[9];
end 

And modified what already existed:

Code: Select all

always @(posedge sys_clk_i) begin
   if (sys_rstn_i == 1'b0) begin
      led_reg[7:1] <= 7'h0 ;
      exp_p_dat_o  <= 8'h0 ;
      exp_p_dir_o  <= 8'h0 ;
      exp_n_dat_o  <= 8'b11000000;
      exp_n_dir_o  <= 8'b11000000 ;
   end
   else begin
      if (sys_wen_i) begin
         if (sys_addr_i[19:0]==20'h10)   exp_p_dir_o  <= sys_wdata_i[8-1:0] ;
         if (sys_addr_i[19:0]==20'h14)   exp_n_dir_o[5:0]  <= sys_wdata_i[5:0] ;
         if (sys_addr_i[19:0]==20'h18)   exp_p_dat_o  <= sys_wdata_i[8-1:0] ;
         if (sys_addr_i[19:0]==20'h1C)   exp_n_dat_o[5:0]  <= sys_wdata_i[5:0] ;

         if (sys_addr_i[19:0]==20'h30)   led_reg[7:1] <= sys_wdata_i[8-1:1] ;
      end
   end
end

This code sets pins DION7 and DION6 to high level after reset, and it works correctly. Also, I've tried to set pins to low level in my "always @" block like

Code: Select all

always @(posedge sys_clk_i) begin
    exp_n_dat_o[7] <= 1'b0;
end 

and it also worked.

The problem is the generator does not work, so I'm only able to set constant states of pins. Is something wrong with my code or am I missing something?

Thanks,
Alex.

[Nils Roos]

Hi Alex,
There is something wrong with your code. Xilinx synthesis really does not like assignments to one register from more than one "always" block, and in reaction optimizes away all but one of the paths. You can find the message about the optimization in the log output of the synthesis run - you may need to increase the per-message logging limit to see it (execute "set_param messaging.defaultLimit 10000" from the tcl console).

The "initial" block poses no problem since it is ignored by synthesis.

[amvasil]

Hi Nils!

Thank you very much for your help!

Merging everything in one always block solved the problem.