Synchronize FPGA DAC ADC and slow ADC

[Fluktuation]

Hello,

I got question adressing the synchronization of the fast ADC DAC and the slower DACs. I try to generate a waveform on the fast DAC and aquire with the fast ADC the response from a system. However, the phase of the data is very important to me. I want to mix down the acquired data with the frequence of the fast DAC and only acquire a small bandwith and complex data points (sin + cos). Therefore, the timing between DAC and ADC should remain the same (when repeating the measurement). Is this possible by using the standard modules of the fpga and the triggering?
The second point adresses the slow DAC. I want to apply slowly changing volts while the fast DAC plays out the waveform, therefore the timing between the fast and the slow DAC is also important. However, as far as I understand the description, the slow DAC is connected to the microcontroller and can't be controlled by the FPGA. Therefore, I can not get a constant timing between both DACs?

thank you in advance

[Nils Roos]

Hi

Therefore, the timing between DAC and ADC should remain the same (when repeating the measurement). Is this possible by using the standard modules of the fpga and the triggering?

The scope's trigger mode 8 allows you to start an acquisition with a fixed (small) delay with respect to the start of the DAC's generated waveform. The clock for the fast DAC is generated by a PLL from the ADC clock, so repeatability should be excellent.
(The delay between generated signal and start of acquisition is caused by the clock synchronizer on the trigger input and is a constant 3 cycles of the 125MHz ADC clock.)

The second point adresses the slow DAC. I want to apply slowly changing volts while the fast DAC plays out the waveform, therefore the timing between the fast and the slow DAC is also important. However, as far as I understand the description, the slow DAC is connected to the microcontroller and can't be controlled by the FPGA. Therefore, I can not get a constant timing between both DACs?

The slow DAC is operating on one of the fast DAC's clocks, so the phase relationship between fast and slow DAC is guaranteed. However, there is no internal mechanism to preload a waveform into the slow DAC. You would need to observe the progress of the fast DAC and write the data for the slow DAC in sync with that from the linux side. This will be susceptible to non-deterministic timing of linux due to context switches etc.

[Fluktuation]

Thank you very much for the fast answer. Is there a possibility to trigger the fast ADC and DAC with the slow DAC (which would allow in combination with a buffered stream for the slow DAC) a deterministic timing between the linux and the FPGA side. Maybe I could use the additional digital input which is afaik directy connected to the FPGA?

[Nils Roos]

The biggest problem you are facing is that there is no readily available method to put samples to the slow DAC in sync with its update cycle.

The slow DAC is freerunning on an external clock and the ARM cores have no way of knowing when a new sample will be read from the data register. Moreover, due to the two systems running from different clock-sources they are inherently difficult to keep in sync.

One option would be to equip the slow DAC with a signal generator module like the fast DAC has. Once the ARM cores don't need to care about synchronisation with the ADC clock, everything becomes much easier, because the ADC, fast DAC and slow DAC run with a fixed phase relationship by design.

[Fluktuation]

>>One option would be to equip the slow DAC with a signal generator module like the fast DAC has. Once the ARM >>cores don't need to care about synchronisation with the ADC clock, everything becomes much easier, because the >>ADC, fast DAC and slow DAC run with a fixed phase relationship by design.

These are great news, in my understanding this means I can write some HDL code and control the module from the FPGA side?
=> The FPGA is connected to the slow DAC?

[Nils Roos]

=> The FPGA is connected to the slow DAC?

The FPGA is the slow DAC. Here (red_pitaya_analog.v:243) is the logic for generating the PWM signal. The only external part of the slow DAC is the averaging filter.

If you are not above a little bit of HDL tinkering, you can rig all three modules to start running simultaneously on the flip of a bit in some register that's accessible to the ARM, or on an external trigger input or, or, or.