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Initial FPGA Build Issues
Posted: Wed Jan 28, 2015 5:12 am
by dsan
Hello all,
I am having an issue getting the example base FPGA code up and running. What I am attempting to do is compile the FPGA code from the git-repo and then use the resulting red_pitaya_top.bin file rather than the boot.bin file from the dropbox sd card zip.
I successfully downloaded the git repo and compiled the FPGA code using Vivado 13.3 on an Ubuntu platform.
The resulting red_pitaya_top.bin file is 2,023kb.
However, the boot.bin file from the drop box location listed in the manual is 2,370kb.
I was expecting these to be the same size. Can someone please help?
Thank you,
Dave
Re: Initial FPGA Build Issues
Posted: Wed Jan 28, 2015 2:16 pm
by Nils Roos
Hi Dave,
The compiled fpga code is just one of three components that make up the boot.bin file. The other two are the first stage boot loader (fsbl) and the u-boot (second stage-) boot loader.
If you want to test your compiled fpga design, you can convert it into a prom file and load it from the console via /dev/xdevcfg (see eg
this thread).
If you want the new design to be active at boot-time you need to build it into the boot.bin and replace the one on the SD card. To just create the boot.bin you can make the target "build/boot.bin" from the Red Pitaya top level directory.
Cheers
Nils
Re: Initial FPGA Build Issues
Posted: Thu Jan 29, 2015 10:54 pm
by dsan
Thanks Nils, that worked perfectly.
Dave
Re: Initial FPGA Build Issues
Posted: Tue Jun 16, 2015 12:20 pm
by willsor
Apologies for the necro, but I'm in a similar situation so I thought a new thread might be excessive.. Nils, how exactly does one 'build the FPGA bin file into the boot.bin" to get the fpga bin file to auto run at startup. I am working on windows, using Vivado, and used win scp with it's built in command line to transfer the fpga.bin file to xdevcfg to get it to run once
Cheers
Re: Initial FPGA Build Issues
Posted: Wed Jun 17, 2015 9:39 pm
by Nils Roos
You need the before-mentioned three components (fsbl.elf, red_pitaya_top.bit and u-boot.elf) to generate a new boot.bin.
The tool to build the boot.bin is included in the Xilinx SDK.
Once you have the three components ready, execute the following (add paths as neccessary)
Code: Select all
<path to SDK>\2013.3\settings64.bat
echo img:{[bootloader] fsbl.elf red_pitaya_top.bit u-boot.elf} > b.bif
bootgen -image b.bif -w -o i boot.bin
If you can't - or don't want to - build the fsbl and u-boot yourself, you can try decomposing the original boot.bin.
There is no "official" way to do that, but I had a look around, and it seems that the code in
this repository, specifically dumpbootbin.c and bootdef.h, would do the right thing.
The code takes a boot.bin and separates it into it's constituent partitions. The generated files xxdump[1..3].dump should be the fsbl, bitstream and u-boot (in that order).
Re: Initial FPGA Build Issues
Posted: Thu Jun 18, 2015 9:53 am
by willsor
Sorry, but where exactly do I find these files fsbl.elf and u-boot.elf.. ?
I'm quite new to the red pitaya, and the only thing I've really familiar with is writing Verilog, I'm quite lost when it comes to booting stuff on red pitaya's linux environment
Re: Initial FPGA Build Issues
Posted: Tue Jun 23, 2015 7:26 pm
by Nils Roos
Re: Initial FPGA Build Issues
Posted: Wed Jun 24, 2015 8:19 am
by willsor
Thanks very much for putting those in a zip for me Nils,
managed to get it to work
