How the gain-phase analyzer application is built ?

[PatrickLafont]

I suppose that there is a double phase sensitive detector implemented in the FPGA which allows to recover the real and imaginary part of the input signal. I am new to Redpitaya and wonder if there is a list of registers which allows to retrieve demodulated signals, set/reset GPIO, access the auxiliary ADCs and DACs. Could anyone give me a quick tutorial ? Thank you.

[Nils Roos]

I suppose that there is a double phase sensitive detector implemented in the FPGA which allows to recover the real and imaginary part of the input signal.

You suppose wrongly, the GPIanalyzer operates on the sampled time domain signals, using only standard scope and signal generator functionality. The complex signal is calculated from both channels in postprocessing.

I am new to Redpitaya and wonder if there is a list of registers which allows to retrieve demodulated signals, set/reset GPIO, access the auxiliary ADCs and DACs.

Here is the register map to all relevant hardware registers. The wiki, particularly this section contains some pointers on how these registers work.

[PatrickLafont]

Thank you for your reply and support.
Would you have a project to make the amp/phase detector embedded in the FPGA ? This will increase the processing speed, I guess. It's just multiplication with the sinus & cosinus of the DDS outputs to be added, I think. You already have the lowpass filters.
An application with embedded phase sensitive detector will be strongly appreciated. In addition, if you can rout out the sinus and the cosinus of the DDS to RF output, one can make IQ modulator/demodulator experiences and teaching, this will be perfect !