Hi All,
I am learning verilog as I am going through the RP scope module. I am trying to interpret exactly what the statement "adc_arm_do <= wen && (addr[19:0]==20'h0) && wdata[0] ;" is doing. I believe that it is setting adc_arm_do if the lsb of register 0 is set. But what exactly does (addr[19:0]==20'h0) mean? Does it make the value of the address wire = 0, which then connects the Configuration register to the wire wdata[] and then takes the value of the lsb? I am trying to understand the mechanics of the statement.
Thanks to anyone that can explain.
John
Help with verilog statement
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Re: Help with verilog statement
Let me take that statement apart step by step:
adc_arm_do <= ... means that the right hand side expression is evaluated and the result is assigned to the register adc_arm_do at its next clock cycle. The clock source is declared in the enclosing always-statement, @(posedge adc_clk_i).
The right hand side expression is the logical and of three inputs:
Two explanations:
Each functional block in the Red Pitaya design is tied to an address range on the processor bus - housekeeping to 0x40000000-0x400fffff, scope to 0x40100000-0x401fffff, ... Some logic in red_pitaya_top.v decodes these addresses and asserts the appropriate enable signal (wen=write enable, ren=read enable) of the corresponding block.
The lower 20 bit of the address are connected to the bus 'addr' directly. The expression (addr[19:0] == 20'h0) means: take the bits 19 through 0 (ie all of them) of the bus 'addr' and compare them to the 20bit constant 0x00000. The result is true if they are equal.
adc_arm_do <= ... means that the right hand side expression is evaluated and the result is assigned to the register adc_arm_do at its next clock cycle. The clock source is declared in the enclosing always-statement, @(posedge adc_clk_i).
The right hand side expression is the logical and of three inputs:
- the signal 'wen'
- the condition (addr[19:0]==20'h0)
- bit 0 of the data bus 'wdata'
- the 'wen' signal to the instance scope_i is asserted
- the address 0x00000 is put on the 20bit address bus 'addr'
- the value 1 is put on the 32bit data bus 'wdata'
Two explanations:
Each functional block in the Red Pitaya design is tied to an address range on the processor bus - housekeeping to 0x40000000-0x400fffff, scope to 0x40100000-0x401fffff, ... Some logic in red_pitaya_top.v decodes these addresses and asserts the appropriate enable signal (wen=write enable, ren=read enable) of the corresponding block.
The lower 20 bit of the address are connected to the bus 'addr' directly. The expression (addr[19:0] == 20'h0) means: take the bits 19 through 0 (ie all of them) of the bus 'addr' and compare them to the 20bit constant 0x00000. The result is true if they are equal.
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- Posts: 47
- Joined: Fri Apr 17, 2015 7:38 pm
- Location: Richmond, VA, USA
Re: Help with verilog statement
OK, thank you very much, Nils! That makes perfect sense. I was confusing myself a bit. Now I get it...
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