I am running into an error with a small modification I've made to the FPGA design. For debugging without an oscilloscope, I have rerouted the DAC output to the scope file and added the data to the bus, whilst creating a buffer of 16kb size just like the ADC. Regarding control signals, I am using the same as the ADC since there is a lot of overlap. Write pointer is also the same since updates will occur at the same time.
Anyway, this is the part of the code that breaks everything (actually everything, all web app will display is 404 not found, ssh and serial are also a no-go's)
At the bottom of red_pitaya_scope.v:
Code: Select all
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20'h00048 : begin ack <= 1'b1; rdata <= {{32-25{1'b0}}, set_b_filt_kk} ; end
20'h0004C : begin ack <= 1'b1; rdata <= {{32-25{1'b0}}, set_b_filt_pp} ; end
20'h1???? : begin ack <= adc_rd_dv; rdata <= {16'h0, 2'h0,adc_a_rd} ; end
20'h2???? : begin ack <= adc_rd_dv; rdata <= {16'h0, 2'h0,adc_b_rd} ; end
20'h3???? : begin ack <= adc_rd_dv; rdata <= {16'h0, 2'h0,dac_a_rd} ; end
20'h4???? : begin ack <= adc_rd_dv; rdata <= {16'h0, 2'h0,dac_b_rd} ; end
default : begin ack <= 1'b1; rdata <= 32'h0 ; end