Increase acquisition memory size

[Kev' Ttn]

Hello everyone,

As I understand, with the different codes available in the GitHub, the maximum memory size is of 16384 points for each acquisition channel. Is it possible to increase this size ? Do I modify the FPGA code (Verilog Code) to implement this "functionality" ?

Why do I need this modification ? Because, with this sample rate and this memory size, we can acquire only 131µs of our signal and it is not a "long" time. Do you think we can use the RAM available on the RP to go to an acquisition of 20ms ?

Thank in advance for your help.

Regards.
Kev' Ttn.

PS : Sorry for my English, it is not perfect.

[Kev' Ttn]

Hi everyone,

I will update a little my post. I have found in the Vivavo's project, a varaible 'RSZ = 14' (in scope.v) which means (I hope) that memory size available is on 14 bits (according to the 16384 values), if I compile with "RSZ = 15", it works but after, the FPGA is not enough powerful to be implemented.

Do you know if it is possible tio use the DDR3 RAM of the RP in order to memorize the data ?

Thanks in advance.

[Crt Valentincic]

We already had a discussion about larger acquisition buffer on our old forum: https://redpitaya.zendesk.com/hc/commun ... the-scope-
At the moment it still on a wish list, but I guess that this will have to be implemented soon, since it is really useful feature.

[Kev' Ttn]

Thank you very much for your answer. I did not see this topic before.

I hope it will be done soon

Regards.

[Matthias Weber]

Is it possible to see the 16k memory as a ring buffer and transfer the data to ram or the sd card?

Matthias

[Kev' Ttn]

You can read the data when you use the "acquire" fonction. All values are displayed in the terminal. But if you want to save them into a SDcard or in a USB peripheral, I think, you need to mount the peripheral.

Personnally, I have created a fonction to save all the data (16384 per channel) into a text file. 1 value per line. After I use the scp command to transfer this file to my computer via a ssh communication. It is the only way I found for the moment. Now, I try to use the Ethernet connection to transfert automatically this text file.

But, why do you want to save the data in the RAM ?

[Matthias Weber]

That's what I do, too. But, in the future my desired board should acquire continously data up to some minutes (at 25MHz). That's why the buffer has to be transfered quite fast to any other memory device. Propably one has to consider FPGA programing and building a DMA between the desired devices as you can see e.g. here: https://redpitaya.zendesk.com/hc/commun ... ia-UDP-TCP
Unfortunately I don't have any experience in doing this.

Matthias

[Kev' Ttn]

I understand what you want to do. I want to implement a similar code. I don't know how to modify the FPGA project in order to implement a DMA transfer. I think, with Vivado, you can use an IP to implement this communication bus.

But, in my opinion, if we modify the FPGA code to create a DMA transfer, we are obliged to modify the acquire function to adapt it with the new data bus.

[Matthias Weber]

Currently I try to just get the github FPGA code to compile and send it to the RedPitaya. Afterwards I'd like to start modifying simple parts of the code and work me into the FPGA programming. We'll see what happens

[Kev' Ttn]

If you want to begin, I did some tests.

For example, when you switch on the RP, you have the LED0 which blink with a period of 1s (exactly 981ms mesured with a oscilloscope )

In the RP Vivado project, you have a hk file (for housekeeping) and in this file, you have a part of code for this blinking with led[0] <= led_cnt[26]. If you change 26 for 25, you compile and transfert it on the RP, you will see the LED which blink twice faster.

You can begin with this

Afterwards, I'm not a pro Vivado so ... I learn to use it by little parts