Using both slow and fast ADC's with the PID?

[isaackod]

I'm fairly new to the Red Pitaya and Verilog, so bear with me here.

The project involves a feedback system to center a laser on quadrant dectector, which requires two things:
- Dividing two position voltages by a 'sum' voltage to get an absolute distance measurement of the laser on a detector.
- Using this distance value as the control signal for a PID, feeding back to a mirror which moves the laser. This kills the turbulence.

The problem I'm facing is that I need three analog inputs. Since my feedback bandwidth only has to be in the 10's of KHz, I think using the two fast analog inputs and one slow analog input should be sufficient. I'd like to be able to only alter the verilog code, leaving the higher-level stuff the same as for the regular PID controller.

So the question is, can one read the slow ADC from the PL? Is it straightforward to decimate the fast ADC's to run at the same clock rate as the slow one?
This thread and the block diagram of the analog section of the Verilog code clearly shows slow DAC's, but not ADC's: viewtopic.php?f=14&t=402.
My worry is that the slow ADC's are only accessible from the PS-- If that is the case, can I accomplish the task by modifying the C code?

Any advice would be greatly appreciated! Loving the RP so far.
Isaac

[Nils Roos]

Hi,

well, you needn't worry, the slow ADC's data is readily accessible to the fpga fabric. If you have a look at red_pitaya_ams.v, the registers adc_a_r through adc_d_r contain the current samples on the slow ADC inputs.

These registers operate on the same clock as the pid and scope modules, so you can just wire them up to them. Unless your application needs a slower pid update rate, you don't need to introduce decimation, the slow inputs will just retain the last measured value between updates.

[isaackod]

Thanks Nils, this is exactly what I was looking for!