AWG working

[jpereira94]

Hi,
I'm trying the understand the workings of the AWG/ASG module. The FPGA memory maps mentions 3 address with counter settings (counter wrap, start offset and counter step), considering only the channel A. After taking a look at the generate command line utility code, I can see that the counter wrap values is always defined to 0x3FFF0000 which means that only the "16 bits for decimal" are defined with the value of 0xFFFC meaning that the AWG will only wrap back when it reaches the end of the 16k buffer. Now taking a look at the step value, for a 62MHz sine wave (the maximum), the step value is, again defined only for the 16 decimal bits, 0x7EF9. The start offset is always defined as 0.

As for the detailed specifications, this register settings means that the DAC gets the first value at the buffer position 0x40210000, gets a second value at 0x40217EF9 and a final value at 0x4021FDF2 before wrapping back to the start offset value. Is this how the AWG works? What is the "counter" mentioned in the memory map document and is there a way to see it's current value? Also is the 16K buffer only filled with one period of the desired signal?

I hope someone can clear me up.
Thanks in advance, Pereira

[geggor]

Dear Pereira,

at the moment I am also trying to get a better understanding of the internals of the AWG, not yet an expert.
For the common use case of creating a sinusoidal, the 16k buffer is filled with one period. At every time step a internal counter is increased by the value of the 'counter step'. To find the entry in the buffer to send to the output, the lower 16 bits of the counter are omitted, and only the highest 14 bits are used. If the counter exceeds the 'counter wrap' value, this value is subtracted (actually it is slightly more, 'counter wrap' + 0x10000). I think the 'start offset' value is only used to initialize the counter when the AWG is started. The frequency of the resulting output signal is given by 125MHz * counter_step/(counter_wrap + 2^16). By default the 'counter wrap' value is set to 2^16 (2^14 - 1), so all of the 16k buffer can be accessed. I think the full counter value is not accessible, only the higher bits as 'current read pointer' (at 0x14 for Channel A), which define the entry in the waveform buffer.

hope that helped
Gregor

[Nils Roos]

Hi,
I don't quite follow your math for the step value. When I take the code from generate

Code: Select all

    awg->step = round(65536 * freq/c_awg_smpl_freq * n);
    awg->wrap = round(65536 * (n-1));

and put in freq = 62e6, n = 16384, c_awg_smpl_freq = 125e6, I arrive at step = 0x1fbe76c9 and wrap = 0x3fff0000.

This leads to the read sequence

Code: Select all

buffer address | dac_pnt
0x40210000     | 0x00000000
0x40211fbe     | 0x1fbe76c9
0x40213f7c     | 0x3f7ced92 (here the 'overshoot' in excess of 0x3fff0000 will be carried into the next round)
0x40211f3c     | 0x1f3c645b
...

As Gregor already said, the counter is the internal position (register dac_pnt in red_pitaya_asg_ch.v) - including fractional part - and its most significant 14 bit can be read through 0x40200014 and 0x40200034.

[jpereira94]

Thank you Gregor and Nils.

I still have some questions.

For the common use case of creating a sinusoidal, the 16k buffer is filled with one period.

And in case of an arbitrary waveform? Does the buffer stills get filled with only one period?

At every time step a internal counter is increased by the value of the 'counter step'.

Each time step is 1/125e6 = 8ns?

Nils, I did arrive at those values, but I misread the most significant 14 bits.

Once again thanks.

[Nils Roos]

The arbitrary waveform you supply can be - well - arbitrary
It's just that if you have your waveform consist of more than one period, the generated frequency will be off by a factor equal to the number of periods (eg your waveform consists of 3 periods, then the generated frequency will be thrice as high as you request). Also, you loose time resolution at lower frequencies because there are fewer samples per period to start with.

And yes, the DAC and all signal processing logic inside the fpga is clocked by the ADC clock input, which is 125MHz in the standard configuration (ie not configured for an external clock source).

[jpereira94]

That cleared things up. Thanks you both for the quick answer!