FPGA Filter programming with Verilog

[TheWickedOne]

Hi guys,

Iam new to FPGA programming and using Verilog. What Iam trying to do is to program different types of filters and implement them into the FPGA. The aim is to filter any signal i create with the signal generator.
Iam using the FPGA Tutorial Project and Vivado 2013.3 which is recommended on the Red Pitaya homepage. The big issue i have is not the programming of the filters, but rather which registers and wires i need to use. I just tried to work with the DAC registers, without any big progress.
Could you guys give me some help/advise, so i could figure out the issue.

Thank you in advance.

[Nils Roos]

Hi,

I'd say the best place to insert your filters would be between the ASG output and the summation/clipping stage in red_pitaya_top.v .

Connect the wires asg_a[14-1:0] and asg_b[14-1:0] to your filter, and replace asg_a and asg_b in this code section with your filter_out_a and filter_out_b.

For example:

Code: Select all

wire [14-1:0] filter_out_a;
wire [14-1:0] filter_out_b;

your_filter i_filter_a (
    .clk_i  (adc_clk),
    .rst_i  (adc_rstn),
    .dat_i  (asg_a),
    .dat_o  (filter_out_a)
);
your_filter i_filter_b (
    ...
);

...

assign dac_a_sum = $signed(filter_out_a) + $signed(pid_a);
assign dac_b_sum = $signed(filter_out_b) + $signed(pid_b);

[TheWickedOne]

Thank you really much for your help!

I just wondering if there is any possibility to use the generate function in linux shell while the FPGA image is loaded into the chip. Any suggestions?

[Nils Roos]

Oh, absolutely. When you ssh into the RP, you can load different bitstream files and then call the generate utility, and you can repeat that as many times as you like.

If you want interaction with your filters at runtime - like for example to change the filter coefficients - it would get more complicated. But if you prepare a set of bitstreams with different fixed-coefficient filters, you can load them one after the other via console and test each of them with a generated input signal.

[TheWickedOne]

Unfortunately, its not working for me. When i load the FPGA image to the board i couldn´t use the signal generator via console nor through the web interface. I just dont get any output signal. I also tried it without my implemented filters, so that´s not the problem.

Iam not using whole of the Vivado project from the RP code section. I got some critical warnings and erros using it. After fixing them the testing LED wasn´t flashing and no response from the console happening. The program was just stucked. So i started working with the FPGA tutorial project and added some code sections and files i needed.

My project looks like this:


Maybe that´s the reason the signal generator is not working? Which modules i need?

[Nils Roos]

So i started working with the FPGA tutorial project and added some code sections and files i needed.

The project layout doesn't tell much about your problem. It would be more pertinent to have a look at the code sections you added - or what you didn't add. Without a look at the whole Verilog project I can't really help you.

[TheWickedOne]

I added the following code in red_pitaya_top.v:

Code: Select all

//  DAC arbitrary signal generator

wire  [ 14-1: 0] asg_a       ;
wire  [ 14-1: 0] asg_b       ;

red_pitaya_asg i_asg
(
   // DAC
  .dac_a_o         (  asg_a                      ),  // CH 1
  .dac_b_o         (  asg_b                      ),  // CH 2
  .dac_clk_i       (  adc_clk                    ),  // clock
  .dac_rstn_i      (  adc_rstn                   ),  // reset - active low
  .trig_a_i        (  exp_p_in[0]                ),
  .trig_b_i        (  exp_p_in[0]                ),
  .trig_out_o      (  trig_asg_out               ),

  // System bus
  .sys_clk_i       (  sys_clk                    ),  // clock
  .sys_rstn_i      (  sys_rstn                   ),  // reset - active low
  .sys_addr_i      (  sys_addr                   ),  // address
  .sys_wdata_i     (  sys_wdata                  ),  // write data
  .sys_sel_i       (  sys_sel                    ),  // write byte select
  .sys_wen_i       (  sys_wen[2]                 ),  // write enable
  .sys_ren_i       (  sys_ren[2]                 ),  // read enable
  .sys_rdata_o     (  sys_rdata[ 2*32+31: 2*32]  ),  // read data
  .sys_err_o       (  sys_err[2]                 ),  // error indicator
  .sys_ack_o       (  sys_ack[2]                 )   // acknowledge signal
);








//---------------------------------------------------------------------------------
//
//  MIMO PID controller

wire  [ 14-1: 0] pid_a       ;
wire  [ 14-1: 0] pid_b       ;

red_pitaya_pid i_pid
(
   // signals
  .clk_i           (  adc_clk                    ),  // clock
  .rstn_i          (  adc_rstn                   ),  // reset - active low
  .dat_a_i         (  adc_a                      ),  // in 1
  .dat_b_i         (  adc_b                      ),  // in 2
  .dat_a_o         (  pid_a                      ),  // out 1
  .dat_b_o         (  pid_b                      ),  // out 2

  // System bus
  .sys_clk_i       (  sys_clk                    ),  // clock
  .sys_rstn_i      (  sys_rstn                   ),  // reset - active low
  .sys_addr_i      (  sys_addr                   ),  // address
  .sys_wdata_i     (  sys_wdata                  ),  // write data
  .sys_sel_i       (  sys_sel                    ),  // write byte select
  .sys_wen_i       (  sys_wen[3]                 ),  // write enable
  .sys_ren_i       (  sys_ren[3]                 ),  // read enable
  .sys_rdata_o     (  sys_rdata[ 3*32+31: 3*32]  ),  // read data
  .sys_err_o       (  sys_err[3]                 ),  // error indicator
  .sys_ack_o       (  sys_ack[3]                 )   // acknowledge signal
);




//---------------------------------------------------------------------------------
//
//  Sumation of ASG and PID signal
//  perform saturation before sending to DAC 

wire  [ 15-1: 0] dac_a_sum       ;
wire  [ 15-1: 0] dac_b_sum       ;

assign dac_a_sum = $signed(asg_a) + $signed(pid_a);
assign dac_b_sum = $signed(asg_b) + $signed(pid_b);

always @(*) begin
   if (dac_a_sum[15-1:15-2] == 2'b01) // pos. overflow
      dac_a <= 14'h1FFF ;
   else if (dac_a_sum[15-1:15-2] == 2'b10) // neg. overflow
      dac_a <= 14'h2000 ;
   else
      dac_a <= dac_a_sum[14-1:0] ;


   if (dac_b_sum[15-1:15-2] == 2'b01) // pos. overflow
      dac_b <= 14'h1FFF ;
   else if (dac_b_sum[15-1:15-2] == 2'b10) // neg. overflow
      dac_b <= 14'h2000 ;
   else
      dac_b <= dac_b_sum[14-1:0] ;
end

and these files to my project:
red_pitaya_asg.v
red_pitaya_asg_ch.v
bus_clk_bridge.v
red_pitaya_pid.v
red_pitaya_pid_block.v

Everything else is still like in the tutorial project. (http://redpitaya.com/make-your-app/fpga ... -tutorial/)

[Nils Roos]

Well, you also need to delete the dummy assignments labelled "region 2 connections" and "region 3 connections", lines 326 - 333 in red_pitaya_top.v . They are there to generate valid signals on the open inputs when there is no module connected to the respective region.

[TheWickedOne]

Thank you really much. Its working!

[amin]

Hi TheWickedOne,

It is nice that you can do filter program in your project.
Although this topis is old post, do you still keep your vivado code?
I would be grateful if you could send me your code.
I want to learn about how to implement filter function using your code.


Regards,
Amin