FPGA register map

Applications, development tools, FPGA, C, WEB
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airizar
Posts: 11
Joined: Wed Jul 09, 2014 4:25 pm

FPGA register map

Post by airizar » Thu Jul 10, 2014 7:59 pm

Would it be possible to have more detailed explanation of the FPGA register map loaded by default in the RedPitaya? A description of how the FPGA hardware works, how the data in stored in buffers, how it's read, what is the impact of writing some of the registers, a state machine diagram would be very helpful or a basic software routine to perform the acquisition for example.

hmaarrfk
Posts: 26
Joined: Fri Jun 27, 2014 3:19 pm

Re: FPGA register map

Post by hmaarrfk » Fri Jul 18, 2014 6:42 am

Check the red_pitaya_top.v, it has the information about how the system bus is split off to the different modules.

The monitor program is basically as simple as it gets, although, it might look daunting if you aren't used to seeing system level c.

Crt Valentincic
Posts: 67
Joined: Wed May 28, 2014 12:15 pm

Re: FPGA register map

Post by Crt Valentincic » Tue Jul 22, 2014 8:28 am

A bit better explanation about Red Pitaya FPGA modules can be found here http://wiki.redpitaya.com/index.php?tit ... ifications, but is still work in progress. Let us know which details would you like to understand better and we will try to improve it in the near future.

airizar
Posts: 11
Joined: Wed Jul 09, 2014 4:25 pm

Re: FPGA register map

Post by airizar » Mon Jul 28, 2014 8:10 am

Thanks for your answer.

It would help a state machine diagram that tells you which is the procedure and the sequence of operations and registers you have to manipulate in order to setup and make it work your AG or scope application.
I've manage to figure out how it works by reading the registers description, reading the verilog code and a lot of trial and error, but I think it would be very helpful to describe the sequence of operations needed to make it work the FPGA engine.

Regards

Andoni

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