FPGA programming to sum two fast signals

[pavel]

The project from my previous comment is for the 125-14 board.

I use the ports.xdc constraints file for both 125-14 and 122-16 boards.

The schematics for both 125-14 and 122-16 boards show 16 connections for each ADC channel. Some connections in the 125-14 schematics have negative indices.

It was easier for me to use the same indexes from 0 to 15 for both versions of the boards.

The ADC interface module selects the correct connections based on the value of the ADC DATA WIDTH parameter.

[Illia]

Oh, I see now. So there is no need to change anything, good to know, thanks!

And for those three AXI4-Stream cores you've mentioned, in which order should they be connected?
I suppose Broadcaster and Combiner should go together, but at which point the Adder should be connected? Because it has two slave inputs and one master output and I am not sure where it goes..
Here is the current BD I made

[pavel]

Adder should be connected to the Broadcaster. You could try skipping the Combiner if you only need one DAC output.

Here is how I would connect them:

ADC->Broadcaster->Adder->DAC

[Illia]

Great, thanks!

I see that the broadcaster has aresetn input. Is it enough to link it to the FCLK_RESET0_N output of ZYNQ7 PS or I need to build the entire PS7 hierarchy like in the Frequency counter exemple?

[Illia]

So, I've tried to do it simple and connect with FCLK_RESET0_N, but it shows critical warning when launching the synthesis/implementation, saying that these ports don't match, and gives suggestion to add Processor System Reset module.
I did as suggested, let Vivado do connection automation, and then intuitively linked peripheral_aresetn port of PS Reset to aresetn port of Broadcaster, but still got that warning.
I mean, the synthesis/implementation goes on despite the warning and bitstream is generated in the end, but I doubt it will work correctly

[pavel]

Just connect the areset port of the Broadcaster module to a constant and set the value of the constant to 1.

You will also need to adjust the settings of the modules that you add. The default values are probably not OK.

[Illia]

Thank you very much, Pavel, for your help! Much apreciated.

Eventually, it seems to be working well if you use either the PS Reset or the constant.

You will also need to adjust the settings of the modules that you add. The default values are probably not OK.

Yes, I saw there are several different parameters for Broadcaster, most of which are optional signals, purpose of which I don't really understand. And the product guide for AXI4-Stream modules doesn't really explain their purpose

[pavel]

If you are having trouble using the Broadcaster module, then maybe an easier solution would be to use the Signal Split module from Anton's Frequency Counter tutorial:

http://antonpotocnik.com/?p=519284

Or you could use a simple Verilog module that would split and sum:

Code: Select all

module adder
(
  (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axis:m_axis" *)
  input  wire        aclk,

  input  wire [31:0] s_axis_tdata,
  input  wire        s_axis_tvalid,

  output wire [31:0] m_axis_tdata,
  output wire        m_axis_tvalid
);

  wire [15:0] result = $signed(s_axis_tdata[31:16]) + $signed(s_axis_tdata[15:0]);
  assign m_axis_tdata = {16'd0, result};
  assign m_axis_tvalid = s_axis_tvalid;

endmodule

[Illia]

Actually it seems to be working with default parameters of the Broadcaster module. I'm observing the sum of two identical signals with my oscilloscope.
There is some latency though when increasing frequency of the generated signal.

But I will try to do the same thing with the Signal splitter module from Anton's project to see if there's any change in the final result.

Thank you!

[Illia]

So, I did some testing of my project with different Block Design configurations, using either AXI4-Stream Broadcaster module, Signal split RTL module + AXI4-Stream Adder module, or Split&Add Verilog module suggested by Pavel.

At first, configuration with the Broadcaster seemed to be doing its job, as I observed doubled signal with my osciloscope, sending two identical signals to IN1 and IN2, and reading from OUT1. Then I tried to disconnect an SMA cable from either IN1 or IN2, expecting to read a signal, identical to the generated one, from the output, as I would be doing the sum of a signal with zero. However, that wasn't the case. Disconnecting IN2 had no influency on the outcome and I still had the "sum" on the oscilloscope, while disconnecting IN1 I had no signal at all. So the data from IN2 aka adc_dat_b*i seemed to be completely ignored by Broadcaster. Eventually, I guess, one has to adjust default parameters of the Broadcaster.
I have also tried to send a signal with the opposite phase on the IN2, expecting to get 0 as the result of the sum, but still got doubled signal.

Fortunately, configuration with Signal Splitter from Anton's Frequency counter project + AXI4-Stream Adder and configuration with Split & Add Verilog module, suggested by Pavel, work perfectly well.

Thank you, Pavel, for your comments, advices and time!