Possibility of Self-Contained Signal Filter Testing on 125-14

[sslerose]

Hello,

I am currently working on a research project using a STEMlab 125-14 where the goal is to be able to create and test (and eventually deploy) different data filtration methods for different signals.

Right now I have a trapezoidal filter created by a colleague that I know has been used with success in the past. So, starting from a simple ADC to DAC project provided by pavel (here), I placed it into the block design in between the ADC and DAC as such, let Vivado do its thing, and generated a bitstream without error (note that trap_0 has S00_AXIS data width 16, so it only takes the 16 LSB from the ADC, which I assume is from adc_dat_a_i).

My question is this: can I have this bitstream running on the STEMlab while simultaneously feeding a signal to it from the built in Signal Generator and reading the filtered signal from the built in Oscilloscope? Ideally, I would have a signal from the generator come out of OUT2, into IN1 where it gets filtered and passed out of OUT1, and finally into IN2 where I can read it from the Oscilloscope.

Optionally, I could also try having some way to command a signal generator from the Linux side (as in the Frequency Counter FPGA lesson) and then have some way to view the wave output for analysis.

Thank you in advance for any pointers anywhere within this program.

[pavel]

My question is this: can I have this bitstream running on the STEMlab while simultaneously feeding a signal to it from the built in Signal Generator and reading the filtered signal from the built in Oscilloscope?

These two bitstreams cannot run simultaneously on the same STEMlab board. The only way to get the functionalities of these two bitstreams is to combine them somehow into a single bitstream.

What could be done relatively easily is to change the ADC to DAC project by adding the following:

• DDS module connected to OUT2 to generate sine waveforms with frequency, phase and amplitude controls
• simple trigger logic and memory block to capture ADC samples from IN2
• Jupyter notebook for a very basic user interface with all controls and a matplotlib plot showing the captured signal

Here is a link to an example of such a Jupyter notebook to illustrate what this type of user interface would look like:
https://github.com/pavel-demin/usb104-a ... late.ipynb

What do you think?

[sslerose]

Pavel,

Ok, I figured that was the case. I will definitely try to do this in the future once I get my current build to start working. Thank you for the head start and the original program.

Edit: Created new subject to discuss current build issues.