Data not being processed by custom Verilog filtering module?

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sslerose
Posts: 34
Joined: Sat Nov 26, 2022 12:43 am

Data not being processed by custom Verilog filtering module?

Post by sslerose » Thu Jun 08, 2023 9:23 pm

Hello,

In a previous post I asked about the viability of creating a self-contained signal filtering testbench. After a discussion with Pavel, I realized that wasn't viable. However, I have a problem in need of fixing before their proposed solution can be tested.

Right now I have a trapezoidal filter created by a colleague that I know has been used with success in the past. So, starting from a simple ADC to DAC project provided by pavel (here), I placed it into the block design in between the ADC and DAC as such, let Vivado do its thing, and generated a bitstream without error (note that trap_0 has S00_AXIS data width 16, so it only takes the 16 LSB from the ADC, which I believe is from adc_dat_a_i). All of the source code for the trap core can be found here.

Naively, I assumed this would just work. However, when I hook my STEMlab up to a a function generator, it seems that the signal is simply passing through the filter core (see images).

I did notice in my colleague's repository that there were several other cores that they made that seem to be useful in some way. If you have the chance (or are just curious) feel free to check them out here (trigger core, which I believe is to allow for a double trapezoidal filter, but I'm not quite sure), here (pulse_gen core, which seems to produce a pulse signal at most every other clock cycle, but I don't know how to implement a trigger), and here (exp_decay core, which produces an exponentially decaying signal on a trigger, again I don't know how to operate triggers otherwise this may be useful).

I am very new to all of this, so I am not quite sure where I went wrong. Any pointers would be much appreciated.

I am going to try again starting from the design in the frequency_counter project to see if anything changes, and also play around with the other cores in my colleague's repository. Thank you in advance for any assistance.

sslerose
Posts: 34
Joined: Sat Nov 26, 2022 12:43 am

Re: Data not being processed by custom Verilog filtering module?

Post by sslerose » Tue Jul 18, 2023 2:16 am

Fixed issue using Intel ModelSim to test my build. Found plentiful issues and fixed them.

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