Register interaction in v0.94

[sslerose]

Hello all

I am working on a project based on the v0.94 build that requires user-defined parameters in my custom Verilog module. I achieved a proof-of-concept model a few months ago that used a barebones approach similar to the Stopwatch or Frequency Counter lessons in which I used a memory-mapped GPIO core to define the necessary parameters. However, I would like to use the v0.94 build to take advantage of the API commands to make acquisition and analysis easier. My intended solution was to write to the free register spaces in the v0.94 project (i.e., 0x4600000 to 0x46FFFFF) from the Linux or JupyerLab side and read the registers from my Verilog module. However, I do not know how to do this. I have tried to find two possible solutions, please give me suggestions or pointers:

1. Is it reasonably possible to run a C file that writes to the free register spaces using the I2C protocol and then use Python for the acquisition? If not, does the team intend to add I2C functionality through Python scripts?
2. As another option, could I memory map the free register spaces in v0.94 (in the same way that the GPIOs were mapped in the frequency counter lesson, but without a GPIO core) and read these from my Verilog modules?

A plan B if using v0.94 in this manner is not possible is to create another barebones project and use Pavel's AXI4 Hub. With this, JupyterLab needs access to the corresponding Python package. Is the addition of Python packages possible in the JupyterLab application of the Red Pitaya?

Thank you in advance for any suggestions!

[redpitaya]

Hello sslerose,

We will add the I2C control through Python API in the future.

For the second part, that is possible and you can find examples of how to do this in FPGA by combining these two tutorials:
- How to link the processing system (add custom component to the base project): https://redpitaya-knowledge-base.readth ... ed-counter
- How to configure the addresses: https://lniv.fe.uni-lj.si/redpitaya/ (the oscilloscope project deals with creating registers and then configuring them through a C program)

From the C program point of view, you need to remap the memory, then you can access the registers with the "monitor" command.

Please note that there might be better ways to address this from the FPGA side. This is a simplified approach.

I hope this helps.

[sslerose]

Hello again,

Thank you for the information! My plan at this point is to pass ADC1 data from the PS to my module and then to channel 1 of the oscilloscope module while routing ADC2 data directly to channel 2 of the oscilloscope.

I do have a small follow-up question: can I run both JuptyerLab and the oscilloscope application simultaneously? I would like to use the Python API to generate a test signal and then use the oscilloscope app to interactively view the outputs.

Thank you in advance!