So I set up a sampling scheme of my own via the FPGA and collected samples via the Linux.
The scheme briefly is ADC -> packetizer -> DMA and I'm only taking 1 ADC channel so 16 bits.
As I've come to know and understand, the ADC on verilog outputs the data in 2s compliment so it would suffice to map the destination in memory to an int16_t data type and read the data from there.
However, when I do this all the values I get are consistently positive, be it a sine signal or constant DC.
For example for DC signals the average binary output is
-0.1 V -> ~6700
-0.2V -> ~5250
-0.3V -> ~7900
-0.4V -> ~6450
-0.5 V -> ~5000
-0.6V and below -> 4096
And for positive values,
0.1 V -> ~5490
0.2V -> ~6935
0.3V -> ~4270
0.4V -> ~5730
0.5 V -> ~7180
0.6V and above-> 8191
It's not clear why this is the case as I should generally expect -8192 to 8191 but here we are I suppose. Any manipulations I should make on the C side as I figured since it's 2C there shouldn't be any need. All help would be much appreciated
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