Sampled data is always positive

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nyagaka
Posts: 12
Joined: Wed Jun 07, 2023 5:24 pm

Sampled data is always positive

Post by nyagaka » Tue May 07, 2024 3:55 pm

Hey,

So I set up a sampling scheme of my own via the FPGA and collected samples via the Linux.
The scheme briefly is ADC -> packetizer -> DMA and I'm only taking 1 ADC channel so 16 bits.

As I've come to know and understand, the ADC on verilog outputs the data in 2s compliment so it would suffice to map the destination in memory to an int16_t data type and read the data from there.
However, when I do this all the values I get are consistently positive, be it a sine signal or constant DC.

For example for DC signals the average binary output is
-0.1 V -> ~6700
-0.2V -> ~5250
-0.3V -> ~7900
-0.4V -> ~6450
-0.5 V -> ~5000
-0.6V and below -> 4096

And for positive values,
0.1 V -> ~5490
0.2V -> ~6935
0.3V -> ~4270
0.4V -> ~5730
0.5 V -> ~7180
0.6V and above-> 8191

It's not clear why this is the case as I should generally expect -8192 to 8191 but here we are I suppose. Any manipulations I should make on the C side as I figured since it's 2C there shouldn't be any need. All help would be much appreciated :)

juretrn
Posts: 117
Joined: Tue Nov 16, 2021 11:38 am

Re: Sampled data is always positive

Post by juretrn » Thu May 09, 2024 2:46 pm

Hi nyagaka,
The resolution of the signal may be 10, 12, 14 or 16 bit; depending on the model of Red Pitaya.
Which model do you have?

nyagaka
Posts: 12
Joined: Wed Jun 07, 2023 5:24 pm

Re: Sampled data is always positive

Post by nyagaka » Sun May 12, 2024 1:37 pm

Hey, sorry for the late response. I'm not sure why I never got a notification regarding your response.
In any case, the resolution is 14-bit.

A bit more info, I tested out the scope application on the board (like the bazaar apps) and it sampled and displayed the input just fine so I'm sure the ADCs are fine so I'm honestly just stumped.
I saw some posts on Pavel's github in particular:

https://github.com/pavel-demin/red-pita ... issues/479

which comes very close to what I'm experiencing. I understood that the output of the ADC block from Pavel would be in 2s complement which makes sense but I haven't had any luck.

Any ideas where the error may lie?

nyagaka
Posts: 12
Joined: Wed Jun 07, 2023 5:24 pm

Re: Sampled data is always positive

Post by nyagaka » Sun May 12, 2024 5:40 pm

Image

Find the image of the scope output attached above. I didn't realize it but it's almost identical to the problem from the github link.

juretrn
Posts: 117
Joined: Tue Nov 16, 2021 11:38 am

Re: Sampled data is always positive

Post by juretrn » Wed May 15, 2024 7:37 am

Can you please upload the image to imgur or a similar service?
In any case, you should double check your bit padding to 16 bit. Usually, it is enough to just do sign extension:

Code: Select all

wire [14-1:0] adc_14bit;
wire [16-1:0] adc_16bit;

assign adc_16bit = { {2{adc_14bit[14-1]}}, adc_14bit};

nyagaka
Posts: 12
Joined: Wed Jun 07, 2023 5:24 pm

Re: Sampled data is always positive

Post by nyagaka » Wed May 15, 2024 10:58 am

https://imgur.com/d5ZvWQc

Here's the link to the image on imgur.
This is from a direct connection of the ADC to the DAC. There's like a clipping effect which is also visible in my sampled data. And yea, I fully understand the padding concept. I'm just not getting the results that I was expecting to get is all and I'm stumped.

juretrn
Posts: 117
Joined: Tue Nov 16, 2021 11:38 am

Re: Sampled data is always positive

Post by juretrn » Fri May 17, 2024 9:09 am

Double check that the way you interpret ADC data is correct and that the DAC gets the correct data format. You can verify the correctness of your interpretation using our testbenches:

Code: Select all

make sim PRJ=... MODEL=...
(I have not uploaded the ADC driver files though)

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