ERROR in 250-12 Customer Doc

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ERROR in 250-12 Customer Doc

Post by taylor_levaur » Fri May 06, 2022 6:08 pm

Hey all,

I wrote a bit ago, having issues with board files. I have made sure that all my ADC pins and DAC pins match exactly to the 250-12 Customer Doc.

To check that the two ADC-DAC pairs (i.e. A and B) were identical, no reason they shouldn't be, I used the GPIO to sweep across all possible inputs to the DACs. Both DACs were given the same exact input by the GPIO. The output of each ADC was accessed, again via the GPIO. The output of DAC_A was fed into the input for ADC_A; like for DAC_B and ADC_B. The results show the two pairs are not identical.

I have verified that the ports.xdc file I am using to build the fpga bitstream matches exactly to the customer doc. However, the xdc file provided (found in RedPitaya/fpga/sdc_250/red_pitaya.xdc) does NOT match the customer doc. For some reason, it appears that I cannot upload files to the forum, so I will do my best to show which pins are different between the XDC file provided by RP and the customer doc. As I am only concerned with the two DAC/ADC pairs, I won't worry about any other discrepancies (although I think there may be an error in the LED pinout).

All of the ADC_B data pins, DAC_A data pins, and DAC_B data pins are exactly the same in both the XDC file and the customer doc. There are 8 pins of ADC_A data pins which do not match.

In the Customer Doc, ADA0_P is listed as U13, but the XDC file lists it as Y16.
In the Customer Doc, ADA2_P is listed as Y16, but the XDC file lists it as V12.
In the Customer Doc, ADA4_P is listed as V12, but the XDC file lists it as T11.
In the Customer Doc, ADA6_P is listed as T11, but the XDC file lists it as W14.
ADA8_P and ADA10_P are matching in the XDC file and the customer doc.

In the Customer Doc, ADA0_N is listed as V13, but the XDC file lists it as Y17.
In the Customer Doc, ADA2_N is listed as Y17, but the XDC file lists it as W13.
In the Customer Doc, ADA4_N is listed as W13, but the XDC file lists it as T10.
In the Customer Doc, ADA6_N is listed as T10, but the XDC file lists it as Y14.
ADA8_N and ADA10_N are matching in the XDC file and the customer doc.

We can see that most of the pins listed in the XDC file are merely a binary place value off. So, what are pins U13 and V13 (both pins not mentioned as ADC data pins by the XDC file) connected to, as listed by the XDC file? They are listed as adc_spi_csb for pin U13 and adc_spi_clk for pin V13. The customer doc lists ADC_CLK as pin W14 and ADC_CSB as pin Y14. There is another similar xdc file provided in the same directory (named red_pitaya_v1r0.xdc), which does appear to match the customer doc, however I am already absolutely sure that all of my DAC and ADC data pins match to the customer doc, exactly. So, just using that second "correct" xdc file for the fpga configuration will not change that fact that my two pairs of DACs/ADCs are not identical. I don't believe the calibration is to blame. I am confident that my C codes used to drive the DAC / read the ADC data from the programmable logic are handling the data appropriately, so that is also not the issue. I will do a second round of testing, where I use the "incorrect" pinout provided by the XDC file (not the v1r0 version), and see if the problem is rectified. If the problem is rectified by using the "incorrect" pinout, I would say confidently that the customer doc has a couple errors and needs to be rectified.

I will update once the test concludes. I am taking 10 samples from the ADC for each separate DAC code spaced at 0.4 ms per sample (want to average out outliers and make sure the system has reached a decent steady-state before the ADC sample is taken into the GPIO).


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Joined: Tue Nov 16, 2021 11:38 am

Re: ERROR in 250-12 Customer Doc

Post by juretrn » Mon May 09, 2022 8:49 am

v1r0 is the pinout of the first production version of STEM250.
It looks like the doc was not changed with the later revisions.

Pins U13 and V13 are the SPI CLK and SPI CS pins for the ADC's SPI interface.

We will update the doc soon, thank you for pointing this out.

In the meantime, please refer to FPGA constraint files.

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