Using External Signal as clock to DDS in Vivado
Posted: Wed Jul 20, 2022 8:19 am
Hello,
I am trying to configure my STEMLAB 125-14 board in Vivado 2020.1 using block design averager project of Anton Potocnik. I am taking an external sinewave signal of frequency 25 MHz from ADC sampling at 125 MSPS as input. My aim is to create (sin/cos) outputs of 25 MHz and 50 MHz synchronized to this 25 MHz RF Input and then do IQ demodulation.
For this, I am creating a logic clock using a comparator with input 25 MHz signal. I feed this clock to a clock wizard to create a 125 MHz clock output. This clock is then used in DDS compiler to generate a 25 and 50 MHz outputs separately. When I wish to see the DDS generated waveforms on DAC which is supplied by ADC_CLK, I get a CLK_DOMAIN mismatch error due to two different clocks being used here. I tried to use 3 multi-bit D-flip flop based synchronizer (1st flip flop is fed with clock wizard output clock, and last 2 flip flops are fed with ADC_CLK) which gives me output of 25 MHz and 50 MHz but they are very distorted and appear undersampled because I see stepwise increments.
Can anyone please suggest me a correct way to do this?
I am trying to configure my STEMLAB 125-14 board in Vivado 2020.1 using block design averager project of Anton Potocnik. I am taking an external sinewave signal of frequency 25 MHz from ADC sampling at 125 MSPS as input. My aim is to create (sin/cos) outputs of 25 MHz and 50 MHz synchronized to this 25 MHz RF Input and then do IQ demodulation.
For this, I am creating a logic clock using a comparator with input 25 MHz signal. I feed this clock to a clock wizard to create a 125 MHz clock output. This clock is then used in DDS compiler to generate a 25 and 50 MHz outputs separately. When I wish to see the DDS generated waveforms on DAC which is supplied by ADC_CLK, I get a CLK_DOMAIN mismatch error due to two different clocks being used here. I tried to use 3 multi-bit D-flip flop based synchronizer (1st flip flop is fed with clock wizard output clock, and last 2 flip flops are fed with ADC_CLK) which gives me output of 25 MHz and 50 MHz but they are very distorted and appear undersampled because I see stepwise increments.
Can anyone please suggest me a correct way to do this?