Red Pitaya 125-14: FPGA programming

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DrT
Posts: 6
Joined: Fri Oct 14, 2022 1:00 pm

Red Pitaya 125-14: FPGA programming

Post by DrT » Mon Oct 17, 2022 3:01 pm

Dear Support,

I have a few questions related to 125-14 installation, components, and best practice.

Software:
I followed the instructions on https://redpitaya.readthedocs.io/en/lat ... light=FPGa and installed XILINX and SDK.
_ For my application I would like to program the FPGA with a single program from Xilinx. Can I do that or I need to install all the ecosystem and various other project mentioned? Can I do both? What would it be the best option if I want to have a blanck project?
On your docs, I see how to build the image and ecosystem but not 100% sure about a stand alone FPGA program can you provide a few advices?

Hardware:
_ Following point above, I would like,then, to be able to upload the program to the FPGA.
On the forum and docs there is mention of a 6 pin connector and on the forum viewtopic.php?t=23495 it seems that the advised JTAG has 14 pins and an adaptor needs to be built. Is this correct or do you suggest a difference connector?
Furthermore on the same post it seems that also https://www.xilinx.com/products/boards- ... -ii-g.html is required. Is this correct?
Can you clarify?

_Can you clarify in 3.2.2.3.8. Signal mapping the note and XADC design error? and what are the changes/ implications for unipolar or bipolar inputs?
Thank you for the support.

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Red Pitaya 125-14: FPGA programming

Post by juretrn » Tue Oct 18, 2022 8:57 am

Hi DrT,

I am not 100% sure, but I believe programming your own image through JTAG would be sufficient to get some basic functionality going even without compiling the ecosystem. (but I don't know how that would affect the OS).

A standalone FPGA can be created if you wish. My suggestion is to copy the folder structure from an existing project and renaming it (within fpga/prj). You should leave the .xdc files as they are and copy the top level interfaces to external pins. Also, it would be a good idea to leave the PS (red_pitaya_ps). The rest of the circuit can be then changed at will.
It would be easiest to copy v0.94, remove unnecessary logic and add your own. Your own RTL files should be added to prj/yourProject/rtl.

You can program your own image to the FPGA by saving the image to /opt/redpitaya/fpga. The image can be loaded at startup by editing startup.sh to point to the path of your image.
However, please note that the PS is configured at startup using the configuration of the "logic" FPGA project. If you wish to change that configuration, you will have to recompile the FSBL.

There is no need to program Red Pitaya through JTAG (you can just use /dev/xdevcfg), but if so desired, my recommendation is to use Digilent's JTAG-HS2 which fits Red Pitaya's JTAG pins perfectly and is much cheaper than the Xilinx solution :)

Regarding XADC inputs, I believe the implication is that 7 V on the AI0 .. AI3 pins will result in half of maximum ADC counts in unipolar mode.

DrT
Posts: 6
Joined: Fri Oct 14, 2022 1:00 pm

Re: Red Pitaya 125-14: FPGA programming

Post by DrT » Tue Oct 18, 2022 11:07 am

Thanks,

I will try to apply your suggestions and I am sure I will have more questions as soon as try ;) .

On another note to clarify, I will certainly try to avoid to affect the OS. The reseason I asked is because I might need all the space I can get on the FPGA but for the moment to test that all works is not mission critical. I will try the /opt/redpitaya/fpga route first and discuss the OS situation in the future.

About the XADC a need a few more clarifications. You mean that bipolar is not affected and I need to remove R273 and provide 0.5V ~ 1V common voltage on the E2 connector (as per instructions). What would be the best way to do the second part?

For unipolar, would be possible for me to change the ratio to obtain fullscale? Would that mean to chang the 56kohm with a 30Kohm? Which resistor/s is/are it/those?
Regards.

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Red Pitaya 125-14: FPGA programming

Post by juretrn » Wed Oct 19, 2022 3:12 pm

Problem with XADC inputs is that I'm not really sure how those are supposed to be configured in regard to the resistors. I checked the schematic and it seems to me that my previous post was wrong - AI0 .. 3 will give full scale (1 V on AIFPx pins) when 7 V is hooked up. You can change that scale (e.g. if you expect to measure voltage in the range from 0 to 3 V) by changing the voltage dividers. I believe the formula for calculating a voltage divider is provided in the same segment of the instructions as this warning comes from.

I am not really sure how bipolar mode is supposed to work, but yes, I believe an external reference must be provided on pin E2-11

DrT
Posts: 6
Joined: Fri Oct 14, 2022 1:00 pm

Re: Red Pitaya 125-14: FPGA programming

Post by DrT » Mon Nov 14, 2022 2:20 pm

I started to understand how to make the various steps for programming FGPA, create a web interface and actually loading it.

However I noticed a certain amount of repetition and many files and I would like to check if I did something wrong or what are those.

Let me explain: I copied the v0.94 from RedPitaya/fpga/ of the git hub once the devicetree was completed... (I think).

within this I would expected the src folder to contain the sources... instead the real sources pointed from the red_pitaya_vivado_project_Z10.tcl loaded are in /RedPitaya/fpga/v0.94/prj/v0.94/project/redpitaya.srcs/sources_1/imports/v0.94/rtl/
but I have similar source files in RedPitaya/fpga/v0.94/prj/v0.94/rtl

Can you explain a little bit the file structures of these project/folders e.g. v0.94 that is suggested to be a good project template?

Regards.

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Red Pitaya 125-14: FPGA programming

Post by juretrn » Mon Nov 14, 2022 2:52 pm

The redpitaya fpga folder contains files that are common and project-specific. The common code is located in rtl and rtl_250 (everything named something_250 is for STEM250 board). The constraints are also common and located in sdc.
For most projects, only the top level file and PS wrapper are located within prj/projectName/rtl. The scripts import both the common and project RTL source folders into .srcs. Files from this folder are then used to compile the bitfile.
If you want to add your own projects, add your files to the project folder (prj/projectName/rtl).

DrT
Posts: 6
Joined: Fri Oct 14, 2022 1:00 pm

Re: Red Pitaya 125-14: FPGA programming

Post by DrT » Wed Nov 16, 2022 5:09 pm

I compiled the v0.94 after coping it as test1 (and renaming all the folders v0.94 into test1) as I think was advised as good start point to make my own fpga project.

However after compilation time contraints were not met. total negative slack TNS -2146.744 ns.

Is this normal? I did not change any code.

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Red Pitaya 125-14: FPGA programming

Post by juretrn » Fri Nov 18, 2022 8:53 am

HI,
I know there are a few endpoints that might occasionally fail timing in the latest sources, but 2100 ns TNS is huge. I don't know why such a timing result might happen.

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