Page 1 of 1

Using the slow DAC from FPGA

Posted: Fri Dec 16, 2022 3:47 pm
by fisp
Hello,

I'm currently working in a project where I'm writing my own FPGA program for the Red Pitaya STEMlab 125-14 .
So far using the fast ADC and DAC is working out fine, but I also need to use 2 channels of the slow DAC outputs. I can't find any information in the documentation how to control the output voltage. The FPGA constrains contain 4 "dac_pwm_o" pins, but I can't find out how to design the PWM signal.

By playing around with different PWM signals I was able to generate a saw-tooth-like voltage, but I would like to be able to adjust a stable output voltage between the 0 to 1.8 V. Is there any information available on how to achieve that?

Thanks,
Finn

Re: Using the slow DAC from FPGA

Posted: Fri Dec 16, 2022 5:57 pm
by juretrn
Hi,
the current FPGA implementation uses a PDM-based slow DAC (red_pitaya_pdm). The configuration for this module is 4x 8 bit values, where 0 represents 0 V and 255 is 1.8 V. The output of that PDM is then passed through an RC filter, which should give an appropriate DC signal.

Re: Using the slow DAC from FPGA

Posted: Mon Jan 02, 2023 3:57 pm
by fisp
Hi,

thanks for your fast reply and your hints! I got the slw DAC working.