Redpitaya Forum

hello

I need more than 16 GPIO. Therefore, I am trying to use the SPI as GPIO.

In the constraint file (.xdc), I wrote:

set_property IOSTANDARD LVCMOS33 [get_ports SPI1_MOSI]
set_property SLEW FAST [get_ports SPI1_MOSI]
set_property DRIVE 8 [get_ports SPI1_MOSI]
set_property PULLTYPE PULLUP [get_ports SPI1_MOSI]
set_property PACKAGE_PIN E9 [get_ports SPI1_MOSI]

When I try to generate bitstream, I got error in VOIVADO:

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 105 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SPI1_MOSI[0].


Can you help with that error ?

Thanks

Hamam

Also, I have done this step:

I open .xpr project in vivado
I open the block design
double click on Zynq7 Processing system block
I went to Peripheral I/O pins
I unchecked SPI0 and SP1.

All the MIO ports can be configured by the user, so you only need to disable the special features attached to certain pins, in your case, this is the SPI line.

In the “systemZxx.tcl” script set the following:

CONFIG.PCW_EN_EMIO_SPI0 {0}
CONFIG.PCW_EN_SPI0 {0}
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0}
CONFIG.PCW_EN_EMIO_SPI1 {0}
CONFIG.PCW_EN_SPI1 {0}
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}

And comment the code line:
connect_bd_intf_net -intf_net processing_system7_SPI_0 [get_bd_intf_ports SPI0] [get_bd_intf_pins processing_system7/SPI_0]

The configurable IO pins are available in the PL part, not in the PS, so the constraints in .xdc won’t go through.

The settings of the PL MIO pins can be changed in the block design or registers.
The parameters of these pins in the .tcl script are as follows:

CONFIG.PCW_MIO_10_DIRECTION {inout} \
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ CONFIG.PCW_MIO_10_PULLUP {enabled} \ CONFIG.PCW_MIO_10_SLEW {slow} \

Thank you very much for your help.

I found the file and I have made the change you mentioned. Now I want to access the MIO pin in the PL: I want to
use the SPI pins as input and output to the PL. Can you help me, please by example or documents?