Issues loading .bit file on FPGA

[juretrn]

Which Red Pitaya do you have? And for which model did you build the FPGA image?

After trying some things, I found that I get an I/O error if I use an incorrect image.
Fo example, if you made an image for Zynq 7010, but your model is a Zynq 7020, then the loading fails.

[redpitaya]

Juretr, please correct me if I am wrong, but from the command, Juretr sent loads an FPGA file that ends with .bit.bin, but Mattias, you are loading just a .bin file.

[juretrn]

The fpgautil doesn't care about file endings. It just tries to get the contents of the specified file into the FPGA device. It's just that the files created by our FPGA Makefile get this ending because of how we create them. In general, bit and .bin are very similar, except for the header IIRC.

[Mattias]

Hello,
I use the 7010. In Vivado it is set that both the *.bit and the *.bin file should be built. I can successfully load the *.bit file in the old version with "cat *.bit > /dev/xdevcfg. But I can't load the *.bin file from the same build under OS 2.0 with fpgautil ....
Do I have to set the flags for the FPGA manager beforehand?
What does "Error: Overlay already exists in the live tree" mean?
Thank you for your help,
Mattias

[juretrn]

I see. Then the problem is that your build is probably too old. Because the OS 2.00 uses a different mechanism to load the design, the project must also be compiled slightly differently.
The bin file is generated using the Xilinx "bootgen" tool. Bootgen is a part of Xilinx SDK 2019.1, so you will have to install that if you don't have it.
If SDK is installed, but bootgen is not found, you must add it to PATH:

Code: Select all

.  /path/to/SDK/2019.1/settings64.sh

This tool accepts .bif files and outputs a .bin file that is compatible with fpgautil.
The .bif file must contain the following:

Code: Select all

all:{path/to/file.bit}

Then, bootgen must be called:

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bootgen -image path/to/file.bif -arch zynq -process_bitstream bin

This outputs a file named {original name of bit file}.bin .

This process is already handled within our FPGA Makefile, so perhaps you can adapt your project to be built using that.