Xilinx XADC core

[ansh]

Hi,

I am programming the FPGA on the red pitaya and want to read values from the slow ADC(Analog input). I have been trying to understand how to use the Xilinx XADC core to accomplish this but do not yet understand the Xilinx XADC documentation and how AXI streaming works. If someone could point me to the right resources to learn about it I would be very grateful.

Best,
Ansh

[redpitaya]

Hello Ansh,

I would suggest using the Verilog/VHDL code to create your FPGA program. The Vivado cores are a nice start but might not be very useful for advanced applications. Otherwise, I would suggest looking into the Xilinx documentation.

Also, next time, please post FPGA-related topics under the FPGA topics section

[juretrn]

Hi,
the use of XADC depends on what you are trying to do. Do you just need to read a value every once in a while or do you need to sample it as quickly as possible?
Keep in mind the data rate goes down with the number of enabled channels - the conversion rate is fixed at 1 MSPS and multiple channels are multiplexed into a single converter. This means enabling 4 channels will result in a data rate of 250 kS for each channel.
You can enable the M_AXIS interface and get your values from that - it only has 4 lines: data, channel ID, valid and ready. You can try to find examples on how to use it.
I believe the XADC setup is already done by our software. Otherwise, you will have to write the internal registers as needed.