Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

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sbenjamin
Posts: 10
Joined: Sun Apr 09, 2023 7:22 am

Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Post by sbenjamin » Tue Apr 18, 2023 2:06 pm

Hi,

I'm new to Red Pitaya, and FPGA programming in general.
I own a SIGNALlab 250-12 Red Pitaya board, and I wish to add my own logic to control the E1 GPIO pins at a high rate (amongst other things). To cut the long story short - I was instructed by the RP Support team to copy the Red Pitaya FPGA GitHub repository (https://github.com/RedPitaya/RedPitaya-FPGA), and create the project v0.94_250 using the Vivado HLS 2020.1 Command Prompt, and running the command: vivado -source red_pitaya_vivado_project_Z20_250.tcl -tclargs v0.94_250, which created the v0.94_250 project for me.

I now want to know what steps do I need to take in order to add modules of my own to this project. The Design Sources Tree is much more complex than the one seen in the example FPGA projects done for the STEMlab 125-14 board - namely the LED blink project (https://redpitaya-knowledge-base.readth ... ed-blinker).

I was told that any additional logic needs to be added to the red_pitaya_top.sv module, as opposed to the modifications made to the system.v module for the LED blink example project (which by the way the system.v files in both projects are Read Only, so I don't understand how the LED blink logic was added to the system.v, but anyway...). So if anyone here has an idea how to add the same LED blink logic as in the 1_led_blink example project to my v0.94_250 project I'll be happy to hear you out.

The LED blink logic uses a Binary Counter and a Slice with [FROM:TO]=[26:26], which means taking the logical '1' every 1.07 seconds.
I've added these two IP blocks to my diagram, but I don't know how to assign them, and where in the code.

Thank you,

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Post by juretrn » Wed Apr 19, 2023 9:17 am

LED blink project uses code packaged as IPs. These are generated into the auto-generated system.v file. This is generated from the Block Design part of the circuit.
If you wanted to interface to a block inside BD, you have to interface it to a in / out port and regenerate the BD. You will then see said port with appropriate connections within system.v .
The production RP designs interface to BD through prj/PROJname/rtl/red_pitaya_ps.v . Any new ports need to be referenced there.
Any of your own logic modifications need to be added as a new file to prj/PROJname/rtl . Then, add them as a new module within red_pitaya_top.

sbenjamin
Posts: 10
Joined: Sun Apr 09, 2023 7:22 am

Re: Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Post by sbenjamin » Fri Apr 21, 2023 9:06 am

Dear juretrn,

Thank you for your reply. Re-generating the BD was exactly what I missed and needed to do. Thank you.

I didn't understand however, what you meant by:
juretrn wrote:
Wed Apr 19, 2023 9:17 am
Any of your own logic modifications need to be added as a new file to prj/PROJname/rtl . Then, add them as a new module within red_pitaya_top.
Did you mean that any module I wish to add to red_pitaya_top.sv I need to save under the directory C:\...\RedPitaya-FPGA-master\prj\v0.94_250\rtl_250?

I have yet to try adding the LED blink, but I was wondering if there's a way to choose the "led_o" from a list (because it should be there) when creating a new Port on the BD, rather than typing "led_o" manually under the Port name field?

Thanks again, and I will let you know how it goes.

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Post by juretrn » Mon Apr 24, 2023 8:34 am

sbenjamin wrote:
Fri Apr 21, 2023 9:06 am

Did you mean that any module I wish to add to red_pitaya_top.sv I need to save under the directory C:\...\RedPitaya-FPGA-master\prj\v0.94_250\rtl_250?
Exactly so.
sbenjamin wrote:
Fri Apr 21, 2023 9:06 am
I have yet to try adding the LED blink, but I was wondering if there's a way to choose the "led_o" from a list (because it should be there) when creating a new Port on the BD, rather than typing "led_o" manually under the Port name field?
I haven't seen that yet. The only drop downs I can recall are for the port type (clock, trigger, bus...).
You can name the port whatever you like anyway.

sbenjamin
Posts: 10
Joined: Sun Apr 09, 2023 7:22 am

Re: Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Post by sbenjamin » Sun Apr 30, 2023 3:17 pm

Dear juretrn,

Thank you for your reply.

Please excuse my ignorance, but I'm receiving the following implementation error:
[DRC MDRV-1] Multiple Driver Nets: Net ps/system_i/<const0> has multiple drivers: ps/system_i/GND/G, and i_hk/led_o_reg[0]/Q.

I assume it's to do with the fact that both i_hk (red_pitaya_hk.v) and ps (red_pitaya_ps.sv) make use of the led_o output (?).

How do I implement then the LED Blink in this project, using the same implementation made through the BD like in the above RP Example I mentioned?

Thanks,

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Post by juretrn » Thu May 04, 2023 7:56 am

It sounds like you have multiple sources for one of the LED bits, specifically on bit 0.

I will assume you are basing this on v0.94_250.
There, you will need to add a bit to interface what is coming from PS.

Code: Select all

 
 wire ps_led; 
 ... 
 PS declaration
 ...
 .led_port(ps_led),
 
and make sure you remove one of the bits from the HK module when assigning into led_o, in this case bit 0:

Code: Select all

 assign led_o = {led_hk[7:1], ps_led};  

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