Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12
Posted: Tue Apr 18, 2023 2:06 pm
Hi,
I'm new to Red Pitaya, and FPGA programming in general.
I own a SIGNALlab 250-12 Red Pitaya board, and I wish to add my own logic to control the E1 GPIO pins at a high rate (amongst other things). To cut the long story short - I was instructed by the RP Support team to copy the Red Pitaya FPGA GitHub repository (https://github.com/RedPitaya/RedPitaya-FPGA), and create the project v0.94_250 using the Vivado HLS 2020.1 Command Prompt, and running the command: vivado -source red_pitaya_vivado_project_Z20_250.tcl -tclargs v0.94_250, which created the v0.94_250 project for me.
I now want to know what steps do I need to take in order to add modules of my own to this project. The Design Sources Tree is much more complex than the one seen in the example FPGA projects done for the STEMlab 125-14 board - namely the LED blink project (https://redpitaya-knowledge-base.readth ... ed-blinker).
I was told that any additional logic needs to be added to the red_pitaya_top.sv module, as opposed to the modifications made to the system.v module for the LED blink example project (which by the way the system.v files in both projects are Read Only, so I don't understand how the LED blink logic was added to the system.v, but anyway...). So if anyone here has an idea how to add the same LED blink logic as in the 1_led_blink example project to my v0.94_250 project I'll be happy to hear you out.
The LED blink logic uses a Binary Counter and a Slice with [FROM:TO]=[26:26], which means taking the logical '1' every 1.07 seconds.
I've added these two IP blocks to my diagram, but I don't know how to assign them, and where in the code.
Thank you,
I'm new to Red Pitaya, and FPGA programming in general.
I own a SIGNALlab 250-12 Red Pitaya board, and I wish to add my own logic to control the E1 GPIO pins at a high rate (amongst other things). To cut the long story short - I was instructed by the RP Support team to copy the Red Pitaya FPGA GitHub repository (https://github.com/RedPitaya/RedPitaya-FPGA), and create the project v0.94_250 using the Vivado HLS 2020.1 Command Prompt, and running the command: vivado -source red_pitaya_vivado_project_Z20_250.tcl -tclargs v0.94_250, which created the v0.94_250 project for me.
I now want to know what steps do I need to take in order to add modules of my own to this project. The Design Sources Tree is much more complex than the one seen in the example FPGA projects done for the STEMlab 125-14 board - namely the LED blink project (https://redpitaya-knowledge-base.readth ... ed-blinker).
I was told that any additional logic needs to be added to the red_pitaya_top.sv module, as opposed to the modifications made to the system.v module for the LED blink example project (which by the way the system.v files in both projects are Read Only, so I don't understand how the LED blink logic was added to the system.v, but anyway...). So if anyone here has an idea how to add the same LED blink logic as in the 1_led_blink example project to my v0.94_250 project I'll be happy to hear you out.
The LED blink logic uses a Binary Counter and a Slice with [FROM:TO]=[26:26], which means taking the logical '1' every 1.07 seconds.
I've added these two IP blocks to my diagram, but I don't know how to assign them, and where in the code.
Thank you,