Redpitaya Forum

Hi everyone,

I'm completely new in the realm of FPGA programming and the use of the RedPitaya device. I'm currently trying to use FPGA to sum two fast signals in real time (which presumably show an intrinsic noisy behavior), but I find extremely hard to use Vivado. I feel, though, that it shouldn't be too much complicated to implement that on the RedPitaya...

I would appreciate some tutorials and references to learn, in general, to use the FPGA for signal processing, since I feel that there's not enough literature about its use. I've already tried to understand the example codes available at the RedPitaya site, and seems impossible to me, though I successfully implemented a run them on my device.

Thanks in advance for your help.

Hi,
Red Pitaya has a few introductory texts for Verilog, basic digital circuit concepts and Vivado itself. Did you check them out?

To answer your question, adding two fast signals is a typical application in an FPGA. You don't even really "have to" use Vivado for anything except building your design.
How much of the original functionality of RP would you like to preserve in this design? You can either make your own project from scratch or modify one of our existing ones.

A sum of two signals would look like this :

OK, thanks! I saw the documentation, but I also had problems to grasp the most important things...

By the way, do you know how to identify the GPIOs? I want to use the external connections of the RP to introduce the inputs.

Hi,
PL-side GPIOs are marked as DIOx_P/_N in the schematic:

https://downloads.redpitaya.com/doc//Re ... v1.0.1.pdf

In the Verilog sources, GPIO pins are named exp_p_io and exp_n_io, with the same indexes as the ones in schematic; exp_p_io[0] -> DIO0_P and so on.

Note that these are bidirectional ports that are driven by tri-state buffers, so you will also have to specify the desired direction of the ports.

Hello everyone.

I desided to write in this topic because I am stuggling with the same task - to implement a sum or a difference of two signals (two ADC inputs and one DAC output).

Same as migibagar, I am absolutely new to FPGA programming, using RP and Vivado. I went through the FPGA lessons published on RedPitaya Knowledgebase website and successfully completed first three, but started to have problems and errors with Frequency counter lesson and the ones after it.

Despite having troubles with Frequency counter lesson, I decided to try and use the complete version from RedPitaya Github for my objective as a starter, as its block design already included ADC and DAC in it. I basically removed frequency counter RTL block and some other IP cores that went with it, and left all the rest (ZYNQ PS, ADC, DAC, etc) and tried to see if it's gonna work and I can get a bitstream. Which was not the case (not surprised ).

So my question is, what would be the step-by-step workflow to develop from scratch a Vivado project that would implement signal summing/difference?

Thans a lot in advance

My first advice is to build a design that you can verify it working. Just so you can actually test that you managed to do "something".
The frequency counter example is quite simple. I'm sure it can be modified as is.
Or to start with, just build the original example and load it to your RP.

Once you've got that down, get your idea into code and simulate it first. Only then try to build the design.

Hello again!

So, I went with a simple block design with the idea to send a signal on ADC input IN1 and to obtain the same signal on DAC output OUT1. Basicly to copy signal and to verify that the design/project works.

Here is my block design and here is the duplicated signal I get on my oscilloscope. It is quite noisy for some reason, but it repeats the form and the amplitude of the original signal from generator.

Then I decided to try making a sum of two exactly identical signals sent to IN1 and IN2 using Adder/Substracter IP core. Here is my BD. However, the result I get is not what I expected and I don't understand the reason for this.
Am I missing something in my design?

Thanks in advance!

P.S. I took the constrains .xdc file from Frequency counter project and used auto-generated design wrapper.

Your project has several problems with the ADC and DAC clock signals.

Here is a link to a simple ADC to DAC project for Vivado 2020.2, that I think would be a better starting point:

https://www.dropbox.com/sh/5fy49wae6xwx ... c.zip?dl=1

To sum two signals, you will need to add AXI4-Stream Broadcaster, AXI4-Stream Adder and AXI4-Stream Combiner.

Oh, I see..
Thank you very much, I will check it out!

Hello Pavel!

Thanks a lot again for sharing your project.
I have a question regarding the constrains file ports.xdc.
I see that for ADC you define 16 inputs, while according to scematics of Red Pitaya STEMlab 125-14 there should be 14, and also package pins are different from PR schematics for this board.
I assume you created this project for a different RP board, right?
Just want to be sure I understand correctly.