Fast ADC@125MSPS stored at DDR
Posted: Wed May 10, 2023 1:24 am
Hi guys!
I'm developing a Nuclear Magnetic Resonance experiment, but I'm in a dead-end using my function generator + Picoscope. That's when I jumped to the Red Pitaya, but it's getting harder than I thought...
So, I'd need a custom Verilog module to store N samples @125MSPS at some DDR memory position, triggered by an internal logic, since the signal must be acquired in sync with the signal generated by the DAC. I have no problem with the DAC, since I don't move any data from the DDR: the signal is generated by hardware in the FPGA.
I'm talking about acquiring ADC data for a maximum time of about 2ms, so, about 250kSamples @ 125MSPS. I say this because I took a look at the oscilloscope implemented in the 0.94 bitstream, but it only offers 16Ksamples, not enough.
I don't need any app nor fancy web GUI right now, just my C code to process the stored ADC data and the FPGA bitstream. Actually, I have a C code already working that opens a socket and sends/receives data to a custom C#+WPF software to display some data and control the FPGA.
I only have the Vivado software installed, so I cannot compile custom kernels (I use the default Kernel which comes with the STEMlab 125-14). So, using a SSH terminal connection, I program and compile the C code like I would do with a Raspberry PI.
I've read this topic: viewtopic.php?f=7&t=317, which fits pretty much with my needs, but I see I need a custom kernel. I just wonder if there is any simple example that I could use as a starting point, since it seems quite a pretty straightforward thing to do given the hardware capabilities. I was also looking at the "stream_app", but I'm not sure whether it can store ADC data at 125MSPS to the DDR, and furthermore, I just need to move the raw ADC data to the DDR, not all the functionalities offered by the stream_app.
First thing I tried to do is to create a Verilog module to generate an ADC stream of data, and plug it to the S_AXIS_S2MM of a "AXI Direct Memory Access", connected to the HP0 of the ZYNQ7. All done using IP blocks. Despite configuring the DMA to receive N data, I can just receive the first one. Anyway, it was just a test, since I don't know if that approach is the best one to get the full 125MSPS bandwidth, it seems a bit critical-timing having into account that the DDR works at 533MHz...
Any help would be appreciated. Thank you!
I'm developing a Nuclear Magnetic Resonance experiment, but I'm in a dead-end using my function generator + Picoscope. That's when I jumped to the Red Pitaya, but it's getting harder than I thought...
So, I'd need a custom Verilog module to store N samples @125MSPS at some DDR memory position, triggered by an internal logic, since the signal must be acquired in sync with the signal generated by the DAC. I have no problem with the DAC, since I don't move any data from the DDR: the signal is generated by hardware in the FPGA.
I'm talking about acquiring ADC data for a maximum time of about 2ms, so, about 250kSamples @ 125MSPS. I say this because I took a look at the oscilloscope implemented in the 0.94 bitstream, but it only offers 16Ksamples, not enough.
I don't need any app nor fancy web GUI right now, just my C code to process the stored ADC data and the FPGA bitstream. Actually, I have a C code already working that opens a socket and sends/receives data to a custom C#+WPF software to display some data and control the FPGA.
I only have the Vivado software installed, so I cannot compile custom kernels (I use the default Kernel which comes with the STEMlab 125-14). So, using a SSH terminal connection, I program and compile the C code like I would do with a Raspberry PI.
I've read this topic: viewtopic.php?f=7&t=317, which fits pretty much with my needs, but I see I need a custom kernel. I just wonder if there is any simple example that I could use as a starting point, since it seems quite a pretty straightforward thing to do given the hardware capabilities. I was also looking at the "stream_app", but I'm not sure whether it can store ADC data at 125MSPS to the DDR, and furthermore, I just need to move the raw ADC data to the DDR, not all the functionalities offered by the stream_app.
First thing I tried to do is to create a Verilog module to generate an ADC stream of data, and plug it to the S_AXIS_S2MM of a "AXI Direct Memory Access", connected to the HP0 of the ZYNQ7. All done using IP blocks. Despite configuring the DMA to receive N data, I can just receive the first one. Anyway, it was just a test, since I don't know if that approach is the best one to get the full 125MSPS bandwidth, it seems a bit critical-timing having into account that the DDR works at 533MHz...
Any help would be appreciated. Thank you!