Fast ADC@125MSPS stored at DDR

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beal
Posts: 5
Joined: Wed May 03, 2023 1:49 am

Fast ADC@125MSPS stored at DDR

Post by beal » Wed May 10, 2023 1:24 am

Hi guys!

I'm developing a Nuclear Magnetic Resonance experiment, but I'm in a dead-end using my function generator + Picoscope. That's when I jumped to the Red Pitaya, but it's getting harder than I thought... :?

So, I'd need a custom Verilog module to store N samples @125MSPS at some DDR memory position, triggered by an internal logic, since the signal must be acquired in sync with the signal generated by the DAC. I have no problem with the DAC, since I don't move any data from the DDR: the signal is generated by hardware in the FPGA.

I'm talking about acquiring ADC data for a maximum time of about 2ms, so, about 250kSamples @ 125MSPS. I say this because I took a look at the oscilloscope implemented in the 0.94 bitstream, but it only offers 16Ksamples, not enough.

I don't need any app nor fancy web GUI right now, just my C code to process the stored ADC data and the FPGA bitstream. Actually, I have a C code already working that opens a socket and sends/receives data to a custom C#+WPF software to display some data and control the FPGA.

I only have the Vivado software installed, so I cannot compile custom kernels (I use the default Kernel which comes with the STEMlab 125-14). So, using a SSH terminal connection, I program and compile the C code like I would do with a Raspberry PI.

I've read this topic: viewtopic.php?f=7&t=317, which fits pretty much with my needs, but I see I need a custom kernel. I just wonder if there is any simple example that I could use as a starting point, since it seems quite a pretty straightforward thing to do given the hardware capabilities. I was also looking at the "stream_app", but I'm not sure whether it can store ADC data at 125MSPS to the DDR, and furthermore, I just need to move the raw ADC data to the DDR, not all the functionalities offered by the stream_app.

First thing I tried to do is to create a Verilog module to generate an ADC stream of data, and plug it to the S_AXIS_S2MM of a "AXI Direct Memory Access", connected to the HP0 of the ZYNQ7. All done using IP blocks. Despite configuring the DMA to receive N data, I can just receive the first one. Anyway, it was just a test, since I don't know if that approach is the best one to get the full 125MSPS bandwidth, it seems a bit critical-timing having into account that the DDR works at 533MHz...

Any help would be appreciated. Thank you!

pavel
Posts: 790
Joined: Sat May 23, 2015 5:22 pm

Re: Fast ADC@125MSPS stored at DDR

Post by pavel » Wed May 10, 2023 9:02 am

Out of curiosity, does your project really require 60 MHz bandwidth?

I do not have a project that writes the undecimated ADC samples to RAM. However, I have a project that could be modified to remove decimation. Here is a link to its code:

https://github.com/pavel-demin/red-pita ... design.tcl

It continuously writes to RAM and have a trigger logic. The total number of samples and the number of pre-trigger samples are configurable.

I also have an example project that can be used for some NMR applications:

http://pavel-demin.github.io/red-pitaya ... ulsed-nmr/

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Fast ADC@125MSPS stored at DDR

Post by juretrn » Wed May 10, 2023 10:11 am

Hi,

our stream_app can store 125 MSPS of both channels (just). Be careful that if you really need to work at full rate on two channels, that this pretty much maxes out the RAM bandwidth. The buffer sizes must be of course increased from default because I don't think they can store that much data.

Stream app uses double buffering and can only stream data to/from RAM. That means while DAC does work with this image, it also uses a lot of RAM bandwidth to do so.

Another option is that v0.94 will soon™ offer an option to acquire data into RAM via AXI, like stream_app does right now.

beal
Posts: 5
Joined: Wed May 03, 2023 1:49 am

Re: Fast ADC@125MSPS stored at DDR

Post by beal » Wed May 10, 2023 10:49 pm

Thanks for you responses :) @pavel, it's true that I could reduce a bit the sampling rate, but my NMR signal is resonating at about 18.54MHz, and since the clock frequency is fixed at 125MHz and not a multiple of 18.54MHz, I need as much precision as I can to do what I need to do. Another option I was thinking about, was to move the ADC clock resistors so that the FPGA drives the ADC clock, that way I could use a MMCM to generate let's say 18.54*5 = 92.7MSPS. Anyway, it's quite fast as well.

Knowing that the stream_app can do the trick, I'm gonna try it first, and if I can't I will try to adapt your code :)

@juretrn, I guess I would still need to modify the v0.94, but it also sounds a good option, since I just need a single ADC channel. Do you know when it will be ready?
And just a newby question: since right now I'm using block diagrams, I added the path "RedPitaya-FPGA-master\prj\stream_app\ip\" in the IP Catalog to add the rp_oscilloscope. Was the oscilloscope IP designed to work this way, or pros usually just use pure Verilog without diagrams?

Thanks!

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Fast ADC@125MSPS stored at DDR

Post by juretrn » Tue May 16, 2023 8:01 am

Sorry, I don't know when the new features in v0.94 will be ready.

You can add rp_oscilloscope to a design within a block design (BD) if you like. Said module is used within stream_app's BD. But you can also add it to your design by declaring rp_oscilloscope in your Verilog sources.

beal
Posts: 5
Joined: Wed May 03, 2023 1:49 am

Re: Fast ADC@125MSPS stored at DDR

Post by beal » Fri May 19, 2023 11:30 pm

Nice, thanks! :) Do you know why by default it's used the external ADC clock? Having an internal clock able to provide the same 125MHz frequency to the ADC just changing those 2 resistors, it seems weird to me to use the external one. When the phase between them gets close to zero (which will happen at certain point for sure, since they both are independent) we might have some metastability problems at the interface block where both clocks join, isn't it?

Thanks!

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Fast ADC@125MSPS stored at DDR

Post by juretrn » Mon May 22, 2023 9:42 am

I'm not really sure what do you mean by external ADC clock.

But the ADC clock is used as a reference for our internal PLLs, which have a fixed phase to the ADC clock. The incoming data is sampled (double registered) by the PLL clock.

The clock received from the daisy chain connectors is passed through FPGA to the FPGA_CLK pins. These pins are ignored on the master board (as they are not connected through the resistors). The master uses the onboard oscillator instead. On the slave board, this clock (from master, received on daisy chain) is a reference for the ADC.

beal
Posts: 5
Joined: Wed May 03, 2023 1:49 am

Re: Fast ADC@125MSPS stored at DDR

Post by beal » Sun May 28, 2023 4:34 pm

Sorry, maybe I haven't explained myself quite good. Looking at the schematic we have 2 clocks sources:

1) The PS is using the PS_CLK, which comes from a 33.33MHz oscillator. So, the PS uses this 33.33MHz clock as the PLL input source to generate the 533MHz for the DDR, as well as the 125MHz for the PL (FCLK_CLK0 by default in the processing system block).
2) Then we have the ADC oscillator (with designator Y1), which also generates 125MHz, but it's independent, so for sure it will have a slighly different frequency than the one generated from the 33.33MHz clock source. Maybe it's just 1Hz, but it will be different for sure. So, at some point, both clock edges will fall in the region where the setup/hold time will not meet the required timing specs. Even using 2-cascade registers to prevent metastability, we probably will loose some clock there.

What I don't understand is, why bothering adding an extra oscillator component if apart of increasing the cost, it also might give metastability issues. Soldering the R27 and R28 resistors instead of the R25 and R26 by default, would make that the FPGA provides the 125MHz through the FCLK_P and FCLK_N, then all clock sources would come from the 33.33MHz clock and solve this issue.

Maybe this question should go to the Hardware section, but it seems you know about the topic and it's related with the ADC.

Thanks!

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Fast ADC@125MSPS stored at DDR

Post by juretrn » Mon May 29, 2023 8:12 am

Hi,
In some apps, the FCLKs are used as an AXI bus transfer clock (that reads data from an internal FIFO), but not much else. Pretty much all of the logic is referenced to the ADC clock.
The reason we don't use FCLKs as a reference is that passing a clock through FPGA increases its jitter by a few ps, which would be noticeable in the acquired signal's spectrum. For more info on that, see Zynq 7000's DC and AC Switching Characteristics Datasheet.
Also, external oscillators are as a rule more stable than onboard ones.

Bulova
Posts: 112
Joined: Fri Jan 09, 2015 6:07 pm
Location: Babenhausen/Germany

Re: Fast ADC@125MSPS stored at DDR

Post by Bulova » Tue Jun 06, 2023 5:11 pm

beal wrote:
Wed May 10, 2023 10:49 pm
Thanks for you responses :) @pavel, it's true that I could reduce a bit the sampling rate, but my NMR signal is resonating at about 18.54MHz, and since the clock frequency is fixed at 125MHz and not a multiple of 18.54MHz, I need as much precision as I can to do what I need to do.
Beal,

may I ask you, what kind of media do you want to measure respectively how much is your magnetic flow density?

I also want to make some experiments with NMR, but I am speculating more on the earth field NMR, which generates signals about 2 kHz.

Best regards

Dieter

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