General question about FPGA programming

[ayaqine932001]

Hi everyone,
I'm working on a closed loop laser frequency stabilization project using a RedPitaya. I have to propose two solutions, one using the Pyrpl library and another solution by programming the FPGA by creating a more or less personal architecture. I was able to familiarize myself with the Pyrpl library. However, for the second solution, I don't know if it's possible to create a new architecture from A to Z. I have knowledge in FPGA, verilog and VHDL AND I have programmed some FPGA cards that do not combine CPU and FPGA.I tried to compile some tcl scripts present in the RedPitaya github but Vivado can't compile them and even when I manage to compile a TCl script, only the block diagram is displayed and I can't access to the source files or even access to the constraints file. So I tried to manually add the source files but I notice that the system_wrapper file is missing. My questions are:
1) is it possible to create a new architecture from A to Z? and create myown blocks?
2) What is the XADC used for?
3) To start, I intend to transmit to the dac samples of sinuses present on a ROM, so do I have to modify the constraints file so that I only activate the outputs of the Dac?
Thanks for your help !

[juretrn]

HI,

which repository did you use? FPGA code is now in
https://github.com/RedPitaya/RedPitaya-FPGA

1. Yes, it's possible to do so.
This command

Code: Select all

make PRJ=v0.94 MODEL=Z10

compiles the oscilloscope + DAC FPGA application - assuming your board is STEM125-14.

Using this command

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make project PRJ=v0.94 MODEL=Z10

you can create a Vivado project and open it in the GUI.
The bare minimum to have a usable FPGA design is to copy the I/O intefaces from red_pitaya_top and include red_pitaya_ps. The _ps file includes Zynq's PS and the interface to the AXI bus that enables the use of onboard DDR.
See https://redpitaya.readthedocs.io/en/lat ... /fpga.html for more info on the FPGA build.

2. XADC is used for slow analog input sampling (on the expansion connectors) and should be accessible through the RP's API.

3. You should not have to do anything with the constraints, all of the IO is constrained as it is. Generating a waveform through a BRAM using DDS is already implemented in RP's FPGA and API.