Using High Level Synthesis streaming blocks with the fast ADCs and DACs

[nyagaka]

Hi, (working on a stem lab 125-14 & I also edited out some stuff from earlier)

I begin by describing my setup.

I was implementing an algorithm for real-time signal processing on the FPGA and figured HLS would be my best alternative. I therefore set up some miniature projects to familiarize myself with the HLS tool and the Red Pitaya board. I initially used the DACs and ADCs implemented by Pavel to succesfully pass a signal from the SMA port in to the SMA port out with the jumpers on LV to start off.

I next implemented a HLS block which would half the amplitude of the input signal it takes. This involved implementing the block in C++ which I will detail below. The top interface was the most crucial part where I utilized 2 hls::stream variables , 1 for the input and 1 for the output.

Like this:

Code: Select all

#include "test.h"
void topfunc(hls::stream<myint> &in,hls::stream<myint> &out)
{
#pragma HLS INTERFACE mode=axis port=in
#pragma HLS INTERFACE mode=axis port=out
#pragma HLS INTERFACE mode=s_axilite port=return bundle=ctrl
	myint in2=in.read(); //reading data from input packet
        myint tmpOut = myfunc(in2);
	out.write(tmpOut); //setting data to output packet
}

In "test.h" I implemented the myint datatype as ap_int<14>.

In addition, the function myfunc returns half of the inputted value considering the conversions between offset binary to 2s complement and back to offset binary for the DAC.

My question was should I try using a TLAST signal? since the ADC block has no TLAST signal in its implementation, I figured it would be pointless to have in my HLS block.

Secondly considering the sampling rate of the fast ADCs and DACs is my implementation of the top adequate to avoid any stalls in the design? I figured 1 sample every 8ns to my block would result in 125MSPS which coincides with the speed of the ADCs and DACs but I'm fairly new to this so I would appreciate any guidance on this matter.