HLS application requiring a memory write to ADC before reading

[nyagaka]

Over the last few weeks I've been attempting at implementing a High Level Synthesis algorithm on the RP FPGA for some signal processing applications. I read the entire vitis HLS guide multiple times and implemented my blocks as guided and tried to directly feed my developed blocks from the ADC output block that Pavel implemented but wasn't getting anything at the output.

Therefore, as any good researcher, I dove into the inner workings of the board and similar projects to what I intended (even from other boards like the imperix) and noticed that the ADC data wasn't immediately received by the blocks but was instead first stored in memory then read from memory. This of course seems very counter intuitive as processing the data as it comes in would result in much less latency when compared to all the latency in reading and writing using DMA.

In any case, I was hoping someone here had any clues as to why this might be the case or maybe I've simply misunderstood what I've read.