What the best way is to extract data from a Verilog module using the AXI Stream interface? Using STEMlab 125-14, no extensions.
I currently have a stream of signal data (roughly 20 bits wide) that I want to extract from a custom module intended to filter a signal. This data is scaled, so I would like to be able to divide all the data by a constant factor to get it to the correct scale (I have been told that trying to descale the data in the Verilog module is not ideal, and that it should be done outside of the FPGA for performance, is this correct?).
Currently I have a system that is intended to determine the peak value of the filtered data using a GPIO and Jupyter notebook and spit it out. However, I would ideally like to view the entire filtered waveform using the Red Pitaya's oscilloscope or have the data put into a file that can be used to observe the waveform using another program.
Some clarifying questions:
- I have an exponentially decaying signal being passed to the DAC via AXIS. It is signed and 16 bits wide (only lower 14 bits have data, i.e., max of signal is 16383) and connected directly to the DAC. Will this signal be passed through OUT1?
- I have the ADC connected directly to the filter via AXIS. The filter only accepts 16 bits (signed), so I assume it takes the lower 16 from the ADC which is from IN1?
- Do the ADC and DAC connect without a cable on the board? When I run my program without a connection, I still receive values from my GPIO2_i port even after correcting for the values I assigned to the GPIO2_o. I have the default tri value set to 0x000FFFFF, so the lower 20 bits will be used at input (i.e, be extracted from the modules), correct?
- I did not start from the 0.94 project, is this ok? I started blank, added a ZYNQ7 PS, necessary ports, Pavel's xdc constrains, and my custom modules, see image here. I essentially modeled my project after the Frequency Counter project, as it had a similar use case. It should be noted that I have the resets for all my modules connected to the GPIO, this is intentional as any time I declare some variables in my Python program, my modules must reset.