Event based acquisition using adc_test project
Posted: Tue Jul 18, 2023 11:29 am
Hi,
I procured a Red Pitaya StemLab 125-10 recently. My target goal is pretty simple, send 32kB ADC data from RP to PC running Ubuntu and repeat the same process after every 1ms, leading to data rate = 31.5MHz. I use adc_test project, removed the cic and filter blocks for running at 125MHz and tested continuous capture with 256kB and it works fine. But when I introduced an input flag to ram writer's code, which initiates the capture every 1ms, the master signals m_axi_wready and m_axi_awready becomes 0 and the OS crashes, I added the block below into else part of the always construct I'm using latest ram_writer code with address width 12, fifo depth 2048. My cma memory is 36M as available by default. I am a beginner in AXI and memory concepts, can you help me identify the source of issue.
I procured a Red Pitaya StemLab 125-10 recently. My target goal is pretty simple, send 32kB ADC data from RP to PC running Ubuntu and repeat the same process after every 1ms, leading to data rate = 31.5MHz. I use adc_test project, removed the cic and filter blocks for running at 125MHz and tested continuous capture with 256kB and it works fine. But when I introduced an input flag to ram writer's code, which initiates the capture every 1ms, the master signals m_axi_wready and m_axi_awready becomes 0 and the OS crashes, I added the block below into else part of the always construct
Code: Select all
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_cntr_reg <= 4'd0;
int_addr_reg <= {(ADDR_WIDTH){1'b0}};
end
else
begin
if(~flag)
begin
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_cntr_reg <= 4'd0;
end
...
...
end