High-Bandwidth Averager Project - Question

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TheGeri
Posts: 12
Joined: Wed Sep 13, 2023 12:46 pm

High-Bandwidth Averager Project - Question

Post by TheGeri » Thu Dec 21, 2023 6:17 pm

Good afternoon,

I am working on the Red Pitaya FPGA Project 5 – High-Bandwidth Averager of Anton Potočnik. I have managed to simulate inputs and observe outputs with 1 module, using a testbench, on this project. Now, I would like to simulate multiple modules (which can be interconnected). Do you know how this could be done?

I would appreciate it if someone could help me with this. Thank you all in advance! :)

TheGeri
Posts: 12
Joined: Wed Sep 13, 2023 12:46 pm

Re: High-Bandwidth Averager Project - Question

Post by TheGeri » Fri Dec 22, 2023 5:26 pm

I have successfully fixed this and simulated different modules using a single test bench. However, I now have another question:

I would like to edit this project so that, based on an external signal, I can store data from an input into the BRAM.

Later, using another external signal, I want to retrieve the data from the BRAM and subtract it from other input data, saving the result in a variable. While I’ve managed to save data in the BRAM (editing the code of this project), I encounter issues when attempting to read only the stored data from the BRAM and compare it with the input data.

Specifically, I am unable to read the previously stored data using Port B. Do you have any advice on how to fix this problem, or do you have any idea how it could be programmed?

I would be very grateful if someone could assist me. Thank you very much in advance, and greetings! :P :D

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redpitaya
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Re: High-Bandwidth Averager Project - Question

Post by redpitaya » Wed Jan 03, 2024 3:32 pm

Hello TheGeri,

Sorry for the late reply.

I have not programmed this from the Vivado IP blocks yet, but it should be as simple as defining an array and storing the values inside it. Then, make sure you have a write counter and access to the system bus (set an address where you can read the data from the array). Here is an example of how to do it for 1.04 OS versions:
https://lniv.fe.uni-lj.si/redpitaya/redpitaya-proc2.htm

You can then check the implementation to see whether the data storage was implemented with BRAM (and not DSP). In case it was implemented with DSPs, try to add a register or two before the input (signal delay of 1 CLK) before and after the data storage.

From reading data with a Bash program, sometimes you might need to execute the "rw" command (remount the image for writing) to access/modify particular files.

Best regards,
Miha

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