writing to DDR using AXI-DMA

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nyagaka
Posts: 8
Joined: Wed Jun 07, 2023 5:24 pm

writing to DDR using AXI-DMA

Post by nyagaka » Sat Jan 20, 2024 9:47 pm

Hi, so my problem is as follows.
I've used the Xilinx AXI-DMA to transfer samples from the PS to the PL, process them then transfer them back to the PS succesfully.
Despite the existence of Pavel's AXIS-RAM writer, I wanted to try and write samples from the ADC to the DDR via the Xilinx AXI-DMA.
To do this, I used both the AXIS-Packetizer and a different custom block that generates a tlast signal after N samples have been received.
In my case, the maximum packet size receivable is 16384 so the number of samples comes down to 16383.
In addition, I made use of only 1 ADC channel so my data is 16 bits and thus when giving the DMA Buffer register the length of data to write, I would give in 32768 bytes.

The channel doesn't stop running when I use both my custom tlast generator and Pavel's AXIS-Packetizer (In the sense that when you check the status registers of the S2MM channel, it say the channel is still running). And as a result, when I check the data from where I expect the samples to be, I find nothing (all 0's as I initialized the location with memsets to 0).

Is it possible, that I shouldn't connect (for instance) the Packetizer's reset to the usual "Processor system reset" and that I should reset it myself? (The other tlast generator also similarly has a reset so it should function in the same way)

I'm just curious as to where I'm making a mistake.
If there's anything that isn't clear, do let me know.

Thanks

juretrn
Posts: 110
Joined: Tue Nov 16, 2021 11:38 am

Re: writing to DDR using AXI-DMA

Post by juretrn » Tue Jan 23, 2024 7:47 pm

There are several things to consider in this regard:
- AXI4 supports up to 256 transfers in burst = 2048 bytes at 64 bit data. The number of transfers is specified in AWLEN signal.
- This length is only supported in INCR type of burst - AWBURST = 01
- The size of the bus must be specified in the AWSIZE signal, which specifies 2^n bytes per transfer, and supports up to 128 bytes per transfer. I am not 100% sure, but the bus size from PS to PL (S_AXI_HP) on Zynq 7010 and 7020 can either be 32 or 64 bit.
Make sure you are not overwhelming the RAM as well, it's 1066 MHz DDR3 with a 16 bit interface.

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