New Red Pitaya FPGA simulation environment

[juretrn]

Hello Red Pitaya developers,

I am happy to announce that in the latest release we have made a significant step up in the usefulness of our simulations.
I hope that they will not only be useful during our internal development, but also to those trying to use our existing designs as a basis for their own.
The idea behind this was to have a common framework that is capable of ADC, DAC or GPIO stimulus using stimulus files. The simulation script (red_pitaya_sim.tcl) determines the board model and project. With that information it loads the appropriate settings and tests that are needed to successfully test the design.

These simulations were validated for our most active development projects: oscilloscope+gen (v0.94) and streaming (stream_app).
Simulation projects are setup in a very similar manner to how a GUI project is made:

make sim PRJ=project_name MODEL=model_of_your_RP

The project itself will be located within prj/project/sim. Any output files will be saved there.
The top level bench is located within top_tb20.sv. The tests are located within top_tc20.sv and top_tc20_strm.sv for streaming application.
Various test defines are located within tb_defines.sv.
There is an ADC driver module that can either read a file - adc_source_chX.bin where X stands for the channel number from 0 to 3. There is also the option to generate a ramp signal or a simple sine wave.
The source of the ADC signal can be picked using parameters within tb_defines.sv with parameters:
FILERD -> if set to 1, it reads the source file.
SINE -> if set to 1, it generates a sine wave. FILERD takes priority.
If both are 0, a ramp signal is generated.
It is suggested to use MATLAB or Octave scripts to generate a binary file that writes each value into a separate line. The values must be 16 bit signed for ADC and DAC. 8 bit unsigned must be used for GPIO.

GPIO signals are generated using the same principle, with a .bin file.
DAC buffers are written from a file before starting the user test if so specified. The required files must be named dac_source_chX.

ADC and DAC initialization are already handled with tasks set_adc_init and set_asg_init. Streaming data acquisition is handled by the task set_osc_full.
Oscilloscope acquisition can be either done into BRAMs or through AXI to a "RAM" (not really RAM, but the tests save which addresses were called and what data was saved there).
ADC and DAC results may be saved into text files. The result of ADC triggers is also saved into a separate file.
The format of the file outputs may be changed using defines within tb_defines.sv .

This is just a quick and dirty announcement. We will try to document the existing tests a bit more thoroughly in the future.