How "Frequency counter" example works.

[javiruni10]

Good morning everyone.

I am trying to do a similar implementation to that of the "Frequency counter", or at least i can make use of some of the ADC implementation and usage of that project.

So i would really appreciate to get a better understanding of the frequency_counter.v. Three questions.


1. In frequency_counter.v, data (cut down to 14 relevant bits in line 43), is compared to the threshold. How is that comparison made in verilog? Since it is comparing a 14 bits signal to a parameter which value is wheter -100 or -150.

2. How can i be sure of the range of the ADC? I have read it can be either +-1V or +-20V, but don`t really know how to check which one i am working with. Almost sure i am on +-1V but would be nice to be really know.

3. Does the ADC show whether its value is positive or negative? how?


A final and less relevant question, why does the entire example make use of 32 bits data althought it only make use of 14 relevant bits?


Thanks in advance!!

[juretrn]

Hi,

1. In Verilog "a bit is a bit". The language is weakly typed which makes comparisons and assignments easy when going from one type to another.
The signal "data" is of the type reg signed and as such it can correctly compare signed constants. The various constants are translated into a representative sequence of bits which can then be used by the user logic.

2. I presume you are talking about SignalLab250? In either case, you cannot know directly in the FPGA which range you are in; that is determined by the software.

3. The data from the ADC is signed. The decoding of the data should be done at the top level. I am not familiar with the example logic, but in the official code that is done in red_pitaya_top.v .

4. While the relevant data is only 14 bit, it must be placed onto a standardized AXI4-Stream bus which can then ( probably? again, not familiar with the design) be interfaced to the PS more easily. Also, it does not hurt to have more bitwidth available if you do any processing on the data.
It's also easier to keep all buses the same width so you can reuse interfaces - these can be predefined and all your modules then use the same type of bus.

[javiruni10]

thanks! helped a lot