How "Frequency counter" example works.
Posted: Tue Feb 06, 2024 2:30 pm
Good morning everyone.
I am trying to do a similar implementation to that of the "Frequency counter", or at least i can make use of some of the ADC implementation and usage of that project.
So i would really appreciate to get a better understanding of the frequency_counter.v. Three questions.
1. In frequency_counter.v, data (cut down to 14 relevant bits in line 43), is compared to the threshold. How is that comparison made in verilog? Since it is comparing a 14 bits signal to a parameter which value is wheter -100 or -150.
2. How can i be sure of the range of the ADC? I have read it can be either +-1V or +-20V, but don`t really know how to check which one i am working with. Almost sure i am on +-1V but would be nice to be really know.
3. Does the ADC show whether its value is positive or negative? how?
A final and less relevant question, why does the entire example make use of 32 bits data althought it only make use of 14 relevant bits?
Thanks in advance!!
I am trying to do a similar implementation to that of the "Frequency counter", or at least i can make use of some of the ADC implementation and usage of that project.
So i would really appreciate to get a better understanding of the frequency_counter.v. Three questions.
1. In frequency_counter.v, data (cut down to 14 relevant bits in line 43), is compared to the threshold. How is that comparison made in verilog? Since it is comparing a 14 bits signal to a parameter which value is wheter -100 or -150.
2. How can i be sure of the range of the ADC? I have read it can be either +-1V or +-20V, but don`t really know how to check which one i am working with. Almost sure i am on +-1V but would be nice to be really know.
3. Does the ADC show whether its value is positive or negative? how?
A final and less relevant question, why does the entire example make use of 32 bits data althought it only make use of 14 relevant bits?
Thanks in advance!!