Data misstreatment

[javiruni10]

Hello.

I am developing a little implementation with 125-14.

Until now, i was working with data bus of 32 after the adc operation, which add padding bits and concatenate both adc into a signal, negating the least 13 least significative and adding 3 MSB.

Well i was working with that signal getting it back into its right form and nothing seems to work ok. Then i decided to acquire the supossed signal with an osciloscope. So, i did:

assign test = {S_AXIS_tdata[13], ~S_AXIS_tdata[12:0]};

By that, i was expecting to get the original signal from one of the two ADC and operate with it, but somehow, it introduces noisy spikes, as if the adc values where wrong.

I have tried to directly introduce the ADC data into the DAC and seems to work perfectly, but with the 32 data bus and the assigment above, it is not working. I am using for the DAC the signal generator block to get the rst, selc, wrt and clk (i have also tried using the ADC clk).

What am i doing wrong?

Thanks!

[javiruni10]

here the noisy signal after the assigment https://ibb.co/NYQ6k0D

[juretrn]

Looks like pretty typical MSB error spikes. Also make sure that your MSB is not somewhow lagging by 1 cycle.

As far as the bus assignment goes, try assigning all of the bits above your MSB as well:

assign test = { {32-13{S_AXIS_tdata[13]}}, ~S_AXIS_tdata[12:0]};