125-14 4CH ADC clocking in PL confusion

[fbalakirev]

I tried to make sense of the ADC clocking logic in the 4CH project on the official RedPitaya-FPGA github and I ended up confused. The constraints file there defines a diff clock input adc_clk_i, pins U18,U19, and an output(?) clock adc_clk_o, pins N20,P20.

On the board schematic the pins N20, P20 are connected to the the clock output(!) of the ADC B, so the adc_clk_o actually appears to be and input, rather then output on the PL side.

Then, in the project top wrapper 'red_pitaya_top_4ADC.sv' the adc_clk_o input is commented, while the adc_clk_i input is declared as 2x2 vector, which appears to be twice as large as the adc_clk_i declaration in the xdc file

Could someone please clarify this confusing schema for us?

[fbalakirev]

P.S. I found another constraints file 'red_pitaya_4ADC.xdc' in the folders somewhere, which is not part of the 0.94 Vivado project. Is this the correct set of constrains for 4CH RP then?

[redpitaya]

Hello fbalakierv,

I am moving this to the FPGA section where the FPGA developers can help with an answer. There may be a mistake in the schematics, but I would like to confirm this before making any changes.

[fbalakirev]

I put together a test project based on Pavel's red pitaya notes and I'm recording the 4 channel data, but I feel that I did not tune idelay. Where can I find the 4CH ADC idelay tuning source code in the Red Pitaya git?

[fbalakirev]

I changed the idelaye2 type from "variable" to "fixed" and tried a few different idelay values in the 0 -16 range. I'm getting the data that looks about the same, not depended of the idelay values:




I'm sending a sine wave in and recoding a chunk of data from 4 channels into a FIFO at 125 MSPS, then print the data, a minimalistic design. The 4ch ADC code is mostly a copy-paste from the vendor git.

The signal reads from the correct channel (I tested all 4) and with correct sine wave frequency, but some bits are messed up no matter what.

Do you have any advice?

[fbalakirev]

Looking at the 125-14 4CH hardware schematics it appears that the ADCs' PAR/SER pins are tied to ground, so one need to set ADC DDR mode over SPI. I searched the official github, but have not found any reference to ADC programming. Could someone point point the relevant code out to me?

P.S. never mind, found some code in the hk module.

[juretrn]

Hi fbalakirev,
IIRC the setup of the ADC line delays was quite an annoying process because there is not that much time for the data to settle before a sampling clock arrives, and all bits must be completely steady. When changing the delay you should also think about the phase of the the ADC clock in relation to the data (can be set in 45 degree steps I believe - via the SPI interface)

If you want to set the ADC to DDR you must send the appropriate commands which, as you saw, are within the housekeeping section.

The pins adc_clk_o are not used on the 4 ADC boards. Thank you for pointing this out, that line of code must be deleted. The actual pin constraints are within prj/v0.94/sdc/red_pitaya_4ADC.xdc. Unfortunately, the pinout of 4 ADC is so different that a completely different constraint file must be used.

[fbalakirev]

Hi juretrn,

Thank you for the detailed reply. I was able to program the ADCs to run in DDR mode and I'm getting something that resembles a sine wave input. I do have to swap odd and even bits in the resulted recording:



There're quite a few bit errors as you can see. As I mention I set ideaye2 to fixed value and I tried 0, 4, and 8 taps, but I'm not seeing much change. I'm not even sure if the ideaye2 are functioning. The only thing I checked that idelay control returns ready bit.

Do you happen to know the optimal idelay tap values that work with the ADC programing defaults stored in the hk module? Are all 28 optimal tap values the same or they differ from lane to lane? Do you know where I can find the code that programs idelay tap values for the 4adc model in the Red Pitaya github?

[fbalakirev]

It turns out the official 2.00-30 SD image records the traces full of glitches on the 4CH product. Here I connect a 10 MHz sine wave signal to all 4 inputs in parallel and use a single run mode on the oscilloscope app. The recorded traces are out of phase with each other together with obvious data loss glitches:



I tested using level trigger as well as the external trigger, the glitches show up in both cases. Perhaps someone in the Red Pitaya team is interested in looking into that.

[juretrn]

There was an acquisition logic bug on CH3 and 4 that we fixed in the latest beta build:
https://github.com/RedPitaya/RedPitaya/ ... ANGELOG.md

Maybe you should try flashing the beta 2.00-35?