125-14 4CH ADC clocking in PL confusion

[juretrn]

Hi fbalakirev,
with regard to tap delays, we use the default value of 4.
These can be programmatically changed, but I don't think we support that in the API. That is mostly an FPGA development thing that SW does not have to mess with. It is also not in the officially listed registers. (sorry :/ )
You can find them in the housekeeping module (red_pitaya_hk_4adc.v); offset 0x40000000
All of the values are 8 bits and are named idly_xxx .
There are 4 registers, one for each channel:
Channel 1 at 0x48
Channel 2 at 0x4C
Channel 3 at 0x50
Channel 4 at 0x54

Writing 0xffffffff to each register increments its tap delay by 1.
You can see the current tap delay by reading the same register.

Code: Select all

root@rp-f0a6b1:~# monitor 0x40000048
0x00000004
root@rp-f0a6b1:~# monitor 0x40000048 0xffffffff
root@rp-f0a6b1:~# monitor 0x40000048
0x00000005

Sorry for my late reply!

[fbalakirev]

Thank you for the info juretrn. It's nice to hear that it's a known bug that you fixed already.

I saw the register tap programming logic in the hk module, and I played around with a different way of programming variable taps. It seems that the 'data eye' is relatively wide in terms of tap values, so I just switched to fixed taps. Its seems that it is also possible to stream all four inputs at full 1 GB/s rate into RAM buffer as large as ~256 MB without data loss using Pavel Demin's Red Pitaya Notes framework.

[redpitaya]

Yeah, we had some acquisition glitch issues in the Oscilloscope application for channels 3 and 4 on the 4-Input. They are fixed in the 2.00-35 Beta version of the OS (the glitches are only in the application and should not affect the other measurements).

Thank you for reporting this.