Re: 125-14 4CH ADC clocking in PL confusion
Posted: Fri Apr 19, 2024 9:41 am
Hi fbalakirev,
with regard to tap delays, we use the default value of 4.
These can be programmatically changed, but I don't think we support that in the API. That is mostly an FPGA development thing that SW does not have to mess with. It is also not in the officially listed registers. (sorry :/ )
You can find them in the housekeeping module (red_pitaya_hk_4adc.v); offset 0x40000000
All of the values are 8 bits and are named idly_xxx .
There are 4 registers, one for each channel:
Channel 1 at 0x48
Channel 2 at 0x4C
Channel 3 at 0x50
Channel 4 at 0x54
Writing 0xffffffff to each register increments its tap delay by 1.
You can see the current tap delay by reading the same register.
Sorry for my late reply!
with regard to tap delays, we use the default value of 4.
These can be programmatically changed, but I don't think we support that in the API. That is mostly an FPGA development thing that SW does not have to mess with. It is also not in the officially listed registers. (sorry :/ )
You can find them in the housekeeping module (red_pitaya_hk_4adc.v); offset 0x40000000
All of the values are 8 bits and are named idly_xxx .
There are 4 registers, one for each channel:
Channel 1 at 0x48
Channel 2 at 0x4C
Channel 3 at 0x50
Channel 4 at 0x54
Writing 0xffffffff to each register increments its tap delay by 1.
You can see the current tap delay by reading the same register.
Code: Select all
root@rp-f0a6b1:~# monitor 0x40000048
0x00000004
root@rp-f0a6b1:~# monitor 0x40000048 0xffffffff
root@rp-f0a6b1:~# monitor 0x40000048
0x00000005