Hello,
I am new to programing FPGA I would like to use the PID module for locking but I see that it accepts only one input. I would like to divide two signals (from in1 and in2), send the quotient as the input to the PID module where I choose a set point and attempt at lock the phase of an interferometer.
Is this doable using PyRPL itself or would I have to build an FPGA image? If so, could someone assist me in modifying the existing FPGA code? As in where I need to write the division stuff and connect the quotient to the PID module?
Thanks in advance
Dividing signals and input to PID
- redpitaya
- Site Admin
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- Joined: Wed Mar 26, 2014 7:04 pm
Re: Dividing signals and input to PID
Hello fpgaSim123,
I am moving this to FPGA-related topics.
Yeah, that sounds doable with PyRPL as you have access to both inputs and pid modules: https://pyrpl.readthedocs.io/en/latest/ ... api-manual. You will have to use OS 1.04-28 or older to work with PyRPL.
You can also check if Linien is useful to you - it does have a PID-only mode (works on 2.00 OS), but it is meant more as a standalone application: https://github.com/linien-org/linien
Since the PyRPL is most likely not going to be maintained by the authors, we are planning to include it in our official OS and fully support it in the future. The problem of it not running on 2.00 OS seems related to Python functions.
I hope this helps.
I am moving this to FPGA-related topics.
Yeah, that sounds doable with PyRPL as you have access to both inputs and pid modules: https://pyrpl.readthedocs.io/en/latest/ ... api-manual. You will have to use OS 1.04-28 or older to work with PyRPL.
You can also check if Linien is useful to you - it does have a PID-only mode (works on 2.00 OS), but it is meant more as a standalone application: https://github.com/linien-org/linien
Since the PyRPL is most likely not going to be maintained by the authors, we are planning to include it in our official OS and fully support it in the future. The problem of it not running on 2.00 OS seems related to Python functions.
I hope this helps.
-
- Posts: 4
- Joined: Tue Apr 16, 2024 9:14 am
Re: Dividing signals and input to PID
Thanks a ton for your reply!
I use OS 1.04 version and while there I could get PID running with PyRPL (after making some changes in the code). I would just like to divide signals and send it to the PID module.
First Question:
I have attempted replacing the PID module with a custom 'adder'' that uses the same register space (please see below) and adds input 1 and input 2. I would like to now try division but the modification from '+' to '/' does not work:
How can I do the division? I get the error:
Second Question:
Once the division is don, how do I connect this output (dat_a_0) as an input to the PID module? Or rather how do I edit the PID module such that this bit can be included? I would later like to choose a setpoint and do the locking using PyRPL. Thanks!
The full adder code:
I use OS 1.04 version and while there I could get PID running with PyRPL (after making some changes in the code). I would just like to divide signals and send it to the PID module.
First Question:
I have attempted replacing the PID module with a custom 'adder'' that uses the same register space (please see below) and adds input 1 and input 2. I would like to now try division but the modification from '+' to '/' does not work:
Code: Select all
division: process(dat_a_i,dat_b_i)
begin
dat_a_o <= dat_a_i / dat_b_i ;
end process;
I even tried using the IEEE.NUMERIC_STD.ALL in the beginning.found '0' definitions of the operator "/".
Second Question:
Once the division is don, how do I connect this output (dat_a_0) as an input to the PID module? Or rather how do I edit the PID module such that this bit can be included? I would later like to choose a setpoint and do the locking using PyRPL. Thanks!
The full adder code:
Code: Select all
--------------------------------------------------------------------------------
-- Author: fpgaSim123
--
-- Design Name: Adder
-- Project Name: Red Pitaya V0.94
-- Target Device: Red Pitaya STEMlab 125-14
-- Tool versions: Vivado 2020.1
-- Description: Input adder code
-- Sys Registers: 403_00000 to 403_fffff (uses MIMO PID register space)
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity adder is
port (
clk_i : in std_logic; -- bus clock
rstn_i : in std_logic; -- bus reset - active low
dat_a_i : in std_logic_vector(13 downto 0); -- input 1
dat_b_i : in std_logic_vector(13 downto 0); -- input 2
dat_a_o : out std_logic_vector(13 downto 0); -- output 1
-- dat_b_o : out std_logic_vector(13 downto 0); -- output 2 // disabled
sys_addr : in std_logic_vector(31 downto 0); -- bus address
sys_wdata : in std_logic_vector(31 downto 0); -- bus write data
sys_wen : in std_logic; -- bus write enable
sys_ren : in std_logic; -- bus read enable
sys_rdata : out std_logic_vector(31 downto 0); -- bus read data
sys_err : out std_logic; -- bus error indicator
sys_ack : out std_logic -- bus acknowledge signal
);
end adder;
architecture Behavioral of adder is
begin
adding: process(dat_a_i,dat_b_i)
begin
dat_a_o <= dat_a_i + dat_b_i ;
end process;
end Behavioral;
- redpitaya
- Site Admin
- Posts: 926
- Joined: Wed Mar 26, 2014 7:04 pm
Re: Dividing signals and input to PID
The easiest way to divide in FPGA is division by a power of 2, where you can just cut the lower bits of a vector to achieve the result super fast and super simple.
The problem is dividing with any other (or custom) numbers as the algorithms that perform the division fast require a lot of FPGA resources, while less complicated solutions take more time/clock cycles.
I recommend checking online for algorithms that perform the division and modifying the bit length to match your specific case (it is not going to be as simple as in higher-level programming languages (like C or Python), where you just add a "/" between two numbers).
For adding your modules to the PyRPL, I would suggest modifying their FPGA image, as it will be compatible with the rest of the PyRPL functionality. Otherwise, you might find yourself in a situation where you have your FPGA code working, but you will not be able to access it inside PyRPL, because it uses a different FPGA image (which is loaded upon application initialisation). Check this link here and go to the Building FPGA firmware link: https://pyrpl.readthedocs.io/en/latest/ ... ation.html
The problem is dividing with any other (or custom) numbers as the algorithms that perform the division fast require a lot of FPGA resources, while less complicated solutions take more time/clock cycles.
I recommend checking online for algorithms that perform the division and modifying the bit length to match your specific case (it is not going to be as simple as in higher-level programming languages (like C or Python), where you just add a "/" between two numbers).
For adding your modules to the PyRPL, I would suggest modifying their FPGA image, as it will be compatible with the rest of the PyRPL functionality. Otherwise, you might find yourself in a situation where you have your FPGA code working, but you will not be able to access it inside PyRPL, because it uses a different FPGA image (which is loaded upon application initialisation). Check this link here and go to the Building FPGA firmware link: https://pyrpl.readthedocs.io/en/latest/ ... ation.html
-
- Posts: 4
- Joined: Tue Apr 16, 2024 9:14 am
Re: Dividing signals and input to PID
Thanks for the reply! I can now successfully divide two signals and view the output on the oscilloscope though I feel like I have to do some calibration.
I would like to now connect the output of this division process as the input to the PID controller. I can see PID_11, PID_12, PID_21 and PID_22. I see that the outputs of PID_11 and PID_12 are summed up as are the other two. Could you please mention where I could include now this division process? Until now I wrote a new module replacing the PID controller. Now I would like to copy the code from the new module and paste it in the PID one where I could connect the output of the division process to the input of the PID module...
And also, the instructions on compiling the FPGA image so as to access it via PyRPL are not clear to me. So I got to the PyRPL directory (I use Anaconda so navigate to Site-Packages and look for PyRPL there) and replace the .bin file over there with the newly generated .bin file by me? And then I just type on the console:
Is this what I have to do?
I would like to now connect the output of this division process as the input to the PID controller. I can see PID_11, PID_12, PID_21 and PID_22. I see that the outputs of PID_11 and PID_12 are summed up as are the other two. Could you please mention where I could include now this division process? Until now I wrote a new module replacing the PID controller. Now I would like to copy the code from the new module and paste it in the PID one where I could connect the output of the division process to the input of the PID module...
And also, the instructions on compiling the FPGA image so as to access it via PyRPL are not clear to me. So I got to the PyRPL directory (I use Anaconda so navigate to Site-Packages and look for PyRPL there) and replace the .bin file over there with the newly generated .bin file by me? And then I just type on the console:
Code: Select all
make red_pitaya_top.bin
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