Redpitaya Forum

Hello,
I am new to red pitaya STEMLab-125-14 board and also to ZYNQ 7000. I know to work on RTL, but not with C programming. I want to transfer the bytes of data from PL logic to DDR3 directly without PS interference. What I understood is that I should use DMA for transfer, but this also uses PS for minimal. And, what I understood from pin package of ZYNQ 7000 series is that the DDR3 IOs are on PS bank.

Is there any help on this? Is there any feasible way to transfer data to DDR3 from PL using RTL without any block diagram approach? At what rate (min and max) the data can be transferred from PL to DDR3 and back to PL?

Thanks

Hi,
with Red Pitaya's hardware configuration, you will have to instantiate the PS to write data to RAM (you need to use S_AXI_HP ports on the PS). There is no other way to access the DDR3. Using these ports does not require any SW intervention. You can instantiate the PS without the block design, but doing that is up to you.

Looking at the Zynq 7000 series in general, you can instantiate a MIG core that can interface a DDR3 chip so that the FPGA fabric can access a RAM. There are no pins on the Red Pitaya to do so.

I couldn't give you a concrete number, but we have successfully implemented 2 channel ADC and DAC streaming - not both at the same time, though.
This gives us 125 MHz*2 channels*2 bytes per samples = 500 MB/s for reading or writing.

Hi,
I made the design using Data mover IP (https://docs.amd.com/r/en-US/pg022_axi_ ... VIuv6BePrw) as shown in the attached file (Block_diagram.jpg). But when I tried reading the data values it is reading alternative values (attached snaps). Why is it so?