FPGA image and Red Pitaya apps

[massimom44]

I wanted to make some modifications to the FPGA to work with the scope+pid app, so I started from the v0.94 (downloaded from https://github.com/RedPitaya/RedPitaya-FPGA.git), made the modifications using Vivado, generated the .bit file and uploaded it to the RP. Then I modified the fpga.conf file in (/opt/redpitaya/www/apps/scope+pid folder) to point to the uploaded fpga image. The scope+pid did start, but it stopped running right away. After some troubleshooting I realized that the issue was not related to the modifications I made, but it seems that the app does not run with the newly generated fpga image even with no modifications at all (same is true for the scopegenpro app). I thought that when you generate an fpga image starting from the v0.94 project, that image would be a clone of the one already in the RP (located in /opt/redpitaya/fpga). I am new to FPGA, so I would need some guidance as to how I can generate an fpga image that works with the web apps.
Thanks,
Massimo

[paracpg]

I suggest you add more information to your post to explain better what versions of the RedPitaya you are using. Here is what I see when I log into my RedPitaya board using the instructions here:

``# cat /etc/lsb-release
DISTRIB_ID=Ubuntu
DISTRIB_RELEASE=22.04
DISTRIB_CODENAME=jammy
DISTRIB_DESCRIPTION="Ubuntu 22.04.4 LTS"

# cat /opt/redpitaya/version.txt
# Red Pitaya GNU/Linux Ecosystem
# Version: 2.00-a0457d3aa
# Build: 37
# Branch:
# Commit: a0457d3aa595ca790b8c4386990f963f775e6c03
# U-Boot: "redpitaya-v2022.1"
# Linux Kernel: "branch-redpitaya-v2024.1"
# Pro Applications: ""
``

[massimom44]

Hi @paracpg,
thanks for the feedback.
Here is what I see when I type the commands you suggested.

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cat /etc/lsb-release
DISTRIB_ID=Ubuntu
DISTRIB_RELEASE=16.04
DISTRIB_CODENAME=xenial
DISTRIB_DESCRIPTION="Ubuntu 16.04.7 LTS"

cat /opt/redpitaya/version.txt
##############################################################################
# Red Pitaya GNU/Linux Ecosystem
# Version: 1.04-93661995d
# Build: 28
# Branch:
# Commit: 93661995dc6c15a706d624bf185f509c48e6b960
# U-Boot: "redpitaya-v2016.4"
# Linux Kernel: "branch-redpitaya-v2017.2"
# Pro Applications: ""
##############################################################################

Also, I am using Vivado 2020.1 to generate the fpga images.

[TheGeri]

Good morning,

I just had the same problem recently but with a newer version. According to the Red Pitaya team:

For 1.04 or older OS versions, you need to get the read/write permission by typing into the command line:

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rw

Then reconfigure the "fpga.conf" file located under:

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/opt/redpitaya/www/apps/scopegenpro/

to point to your custom fpga bitstream file (ending in ".bit"). Finally, remount the SD card back to read only with:

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ro

Using these steps, the FPGA image will be changed just for the
oscilloscope application (each time it is loaded/opened). To return the
oscilloscope functionality back to the original image change the
"fpga.conf" back to:

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/opt/redpitaya/fpga/fpga_0.94.bit

If it keeps happening to you, you can use this command to see what exactly is happening. This is a log when working with web applications:

tail -f /var/log/redpitaya_debug.log

Kind regards,

[massimom44]

Hi TheGeri,
Thanks for your feedback.
What you described is the procedure I was already following (I wasn't issuing the 'ro' command at the end, but that did not make a difference).
Regarding the debug, on my version the /var/log/red_pitaya.log file does not exist. I looked at the log files
/var/log/redpitaya_nginx/error.log
and
/var/log/redpitaya_nginx/debug.log
but they don't have any new entries when the scope app is launched with the cloned fpga image. Last entries in the debug.log file are

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tr: write error: Broken pipe

but they occurred before I launched the scope app.
By the way, this issue (i.e., the apps don't run with a cloned fpga image) also occurs on a second RP board that has the same 1.04 OS version.

Thanks,
Massimo

[TheGeri]

Good afternoon,

I don't know what that line might be related to. From which version of Github are you downloading the apps you want to put? (e.g. scope+pid) Maybe the error comes because the version of the apps is not the same as the ecosystem version...

By the way, this post explains how to do it for version 2.00, in case it can help you to get some ideas: https://forum.redpitaya.com/viewtopic.php?f=14&t=25427

Kind regards,

[massimom44]

Hi TheGeri,
Thanks again for your comments.
I read your postings at the link you provided and I would like to commend you for giving a detailed account of the troubleshooting you went through. That is vary valuable material for people like me who are new to FPGA.
One idea I got after reading your postings was to copy the original fpga image (located in \opt\redpitaya\fpga\fpga_0.94.bit) into the /root folder where the other custom fpga files are. Then I modified the fpga.conf file in /opt/redpitaya/www/apps/scopegenpro to point to the file in the /root folder. The oscilloscope app this time was working.
This seems to indicate that the issue I am having is related to the file generated by Vivado.
As I said, I am using Vivado 2020.1 on Windows. I generated the v0.94 clone starting from the files in the repository https://github.com/RedPitaya/RedPitaya-FPGA/tree/master. I used the Vivado HLS 2020.1 Command Prompt and issued the command

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make project PRJ=v0.94 MODEL=Z10

. Once the project was loaded, I clicked on the "generate bitstream" button and copied the .bit file into the red pitaya. For some reason, this file is not a clone of the original fpga_0.94.bit. Their sizes are also different (the cloned one is about twice as large). Any comments?

[TheGeri]

Good morning massimomm44,

Thank you very much, I am also new to FPGA (and RP!) and I am learning a lot here. Have you looked (I am sure you have) at this example?

https://redpitaya-knowledge-base.readth ... unter.html

I think you could program the FPGA with your own bitstream file located in the /root/ folder of Red Pitaya. To program the FPGA you can run the following line in the Linux console of your Red Pitaya:

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redpitaya> cat Led_counter.bit > /dev/xdevcfg

With this you can check if the bitstream file is loaded correctly on the board and if the problem really comes from Vivado.

Best regards,

[juretrn]

For some reason, this file is not a clone of the original fpga_0.94.bit. Their sizes are also different (the cloned one is about twice as large). Any comments?

Observe what happens in the TCL console when you click "write bitstream" in the GUI versus what our scripts do.
I am pretty sure the default commands in the GUI are different from what the official build does.
Relying on checking file sizes will most of the time tell you nothing. I can tell you that you can make significant changes to a design and the file size does not change at all, for example.

[massimom44]

Hi juretrn,
Thanks for your comments.
I am attaching files with the Tcl console output, Synthesis and Implementation Reports and the Messages generated by Vivado during the process of loading the project and generating the bitstream.
To make sure the output was not contaminated by a previous run, I downloaded the current FPGA repository from github opened the Vivado HSL 202.1 command prompt went to the redpitaya-fpga-master folder and issued the command

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make project PRJ=v0.94 MODEL=Z10

And then generated the bitstream by clicking on the "Generate Bitstream" button.
I can see that there are a few warnings in the attached logs, but I am not sure how important they are. It would be nice if somebody could have a look at them. Thanks!!