Using the Red Pitaya as a pure FPGA

dedicated to the FPGA topics for all Red Pitaya programmers
molinat
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Joined: Wed Oct 29, 2014 5:27 pm

Using the Red Pitaya as a pure FPGA

Post by molinat » Wed Oct 29, 2014 5:31 pm

I am working for my school’s research group, and we’re planning on using the RP to convert signals from Ethernet to analog signals via the ADC. We would like to bypass the ARM chip, and solely use the FPGA to process the signals. After looking through the Verilog files on Github, and reading how to program the RP, I am still a little lost if reprogramming the SoC can be done so that the FPGA can work as a standalone component without an operating system. If so, is there a way to view how the FPGA pins are connected to all of the components, and what the components are?

Nils Roos
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Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Wed Oct 29, 2014 9:07 pm

It's not entirely clear to me what your goal is, perhaps you could clarify:

Do you not want to use the ARM cores at all, or do you just not want to use them to process your data stream ?

It is possible to put the ARM cores into permanent sleep after the first stage boot loader has initialized the FPGA.
All the embedded hardware blocks (USB controller, ethernet controller, UART, DDR controller, ...) can be accessed through the central interconnect, which also has a path to the FPGA.

But without an OS or equivalent bare metal drivers running on the cores, there is no TCP stack, no nothing, you'd have to do everything in logic. I am not sure that this is what you want.

If, on the other hand, you want to process the received data in the FPGA and then hand them on to the DAC, but are ok with the OS doing the network stuff, that is another matter.

molinat
Posts: 6
Joined: Wed Oct 29, 2014 5:27 pm

Re: Using the Red Pitaya as a pure FPGA

Post by molinat » Wed Oct 29, 2014 11:38 pm

Nils Roos wrote: But without an OS or equivalent bare metal drivers running on the cores, there is no TCP stack, no nothing, you'd have to do everything in logic. I am not sure that this is what you want.
Spot on! I would like to not use the ARM processors or OS at all, but rather use the ADC's and DAC's using pure logic and FIFOs. Is this a possibility using the R P, and if so what resources are there for the pin mapping for the board?

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Thu Oct 30, 2014 3:29 am

A quick rundown of facts:
  1. ADC and DAC are under sole control of the FPGA through a couple of IO pins.
  2. All ZYNQ on-chip peripherals are memory mapped into the central interconnect's address space, and can be controlled by the FPGA through same.
  3. The on-chip peripherals can be mapped to external pins or can remain unconnected, leaving you in control of the external connections.
If you plan to proceed in that direction, I would strongly advise you to get acquainted with the relevant Xilinx documentation, formost the Technical Reference Manual. Armed with that information, you would fire up your preferred Xilinx FPGA tool and take a look at the RedPitaya's PS-IP block "system_i". There you can change the mappings to external pins if you really wanted to control the external hardware from programmable logic.

molinat
Posts: 6
Joined: Wed Oct 29, 2014 5:27 pm

Re: Using the Red Pitaya as a pure FPGA

Post by molinat » Thu Oct 30, 2014 10:27 am

Thank you for pointing me to the reference manual for the SoC chips. I've searched R P's github for the system_i file to view in vivado, but to no avail. Is it located within a different file, or do I need to download the HDL from github and compile it all in Vivado to view the pin mappings?

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Thu Oct 30, 2014 11:20 am

Ah, sorry, that is the instance name within the RedPitaya project, not a filename. The "system"-subsystem is a block design and consists of a load of separate files.

With the RedPitaya project open, just select "Open Block Design" on the left. In the schematic that is shown then, double-click the central block. That opens the IP-customization dialog, where you can change all the details of the ZYNQ on-board hardware.

You can also find the "system"-subsystem when you navigate to red_pitaya_top -> red_pitaya_ps -> system_wrapper -> system.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Thu Oct 30, 2014 3:47 pm

One more thing: you can find the details of the ADC / DAC / E1 / E2 connections in red_pitaya.xdc (not the schematics, but the IO configuration and on which pins they are).

molinat
Posts: 6
Joined: Wed Oct 29, 2014 5:27 pm

Re: Using the Red Pitaya as a pure FPGA

Post by molinat » Fri Oct 31, 2014 10:29 am

Nils Roos wrote:Ah, sorry, that is the instance name within the RedPitaya project, not a filename. The "system"-subsystem is a block design and consists of a load of separate files.

With the RedPitaya project open, just select "Open Block Design" on the left. In the schematic that is shown then, double-click the central block. That opens the IP-customization dialog, where you can change all the details of the ZYNQ on-board hardware.

You can also find the "system"-subsystem when you navigate to red_pitaya_top -> red_pitaya_ps -> system_wrapper -> systeIm.

I'm sorry I'm still a little confused. I looked at the GitHub in the file RedPitaya>FPGA>Release1>fpga>code>rtl and found the verilog files pertaining to the RP'sFPGA. Are these the files I should down load and run via Vivado to find the pin mappings and the FPGA internals, or is there different folder containing one complete file?

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Using the Red Pitaya as a pure FPGA

Post by Nils Roos » Fri Oct 31, 2014 1:58 pm

I'm sorry I'm still a little confused. I looked at the GitHub in the file RedPitaya>FPGA>Release1>fpga>code>rtl and found the verilog files pertaining to the RP'sFPGA. Are these the files I should down load and run via Vivado to find the pin mappings and the FPGA internals, or is there different folder containing one complete file?
There is a project file that tells Vivado which components make up the project (the sources from code/rtl are just one part).

It's best to fork - or download and unzip - the whole repository. Even if you don't need the other components, it's always nice to have a working example handy for reference.

The project file for Vivado is "FPFA/release1/fpga/vivado/red_pitaya.xpr". When you start Vivado, select "open project" and point it to this file. Once it's loaded, you can open the block design, etc as previously described.

molinat
Posts: 6
Joined: Wed Oct 29, 2014 5:27 pm

Re: Using the Red Pitaya as a pure FPGA

Post by molinat » Sun Nov 02, 2014 3:51 pm

Ahha! I understand now. Thanks for the tips and reference sources. One more follow up question though. Is there a document showing how the Ethernet port and ADC/DAC are routed to the Zynq chip?

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